PMOS Charge Pump Switching for Low-Resistance Signal Paths
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Solution Overview
Problem
Existing MOSFET switch devices suffer from high on-resistance and on-capacitance, which can distort signals and reduce performance due to undesirable electrical characteristics and stray leakages.
Innovation Solution
The implementation of a charge pump switch apparatus with P-type metal-oxide-semiconductor field-effect transistors (PMOS) and a voltage control circuit that dynamically manages voltages to maintain low on-resistance and on-capacitance, using a charge pump voltage and a voltage selector to optimize the state of the switch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a MOSFET switch device is designed with standard voltage levels, then the device structure is simple and easy to manufacture, but the on-resistance and on-capacitance become relatively high causing signal distortion and performance degradation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage level applied to the MOSFET gate based on the signal frequency. At low frequencies, a standard voltage level (e.g., 3.3V) is applied, while at high frequencies, an elevated voltage level (e.g., 5V or higher) is applied. This dynamic parameter adjustment optimizes the on-resistance and on-capacitance characteristics across different operating conditions, thereby maintaining signal fidelity without requiring a fundamentally different device structure
Solution Approach 2:
The patent implements dynamics by introducing a voltage selector circuit that can switch between multiple voltage levels based on the input signal frequency. The system transitions from a static voltage application approach to a dynamic one where the gate voltage adapts in real-time to the operating conditions. This dynamic adaptation allows the MOSFET to maintain optimal electrical characteristics across varying frequencies, resolving the contradiction between structural simplicity and signal fidelity
2Reliability
If the MOSFET gate voltage is increased to reduce on-resistance and on-capacitance, then signal fidelity improves, but the device complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-establishing a voltage selector circuit with multiple ready-to-use voltage levels (e.g., 3.3V, 5V, and higher). Instead of dynamically generating complex voltage waveforms in real-time, the system prepares multiple discrete voltage levels in advance and simply selects the appropriate one based on the signal frequency. This preliminary preparation reduces the complexity of the control circuit while still achieving the benefit of optimized signal fidelity
Solution Approach 2:
The patent employs a pragmatic approach by using simple, discrete voltage levels rather than complex continuously variable voltage control. The voltage selector circuit uses straightforward switching mechanisms (such as transistor-based switches or relay contacts) to select from pre-defined voltage levels. This approach sacrifices some precision but achieves sufficient performance improvement with minimal added complexity and power consumption
3Use of energy by moving object
If standard voltage levels are used for the MOSFET gate, then power consumption is low and device operation is simple, but on-resistance and on-capacitance cause signal attenuation and delay
Solution Approach 1:
The patent applies partial or excessive action by selectively applying elevated voltage levels only when necessary (i.e., when the input signal frequency exceeds a threshold). For low-frequency signals, the standard voltage level is maintained to minimize power consumption. For high-frequency signals, the elevated voltage level is applied temporarily to ensure adequate signal transmission quality. This selective application of excessive voltage resolves the contradiction between power efficiency and signal quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution maintains signal integrity by reducing on-resistance and on-capacitance, minimizing leakage, and enhancing bandwidth, thereby improving the overall performance of the MOSFET switch device.
Implementation Method 1
a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail
Data Source
AI summary
In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.