Power Amplifier Bias Wiring Layout for Thermal Coupling
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Solution Overview
Problem
Existing power amplifier circuits face inefficiencies due to inadequate thermal coupling between transistors, leading to variations in gain and heat management issues during RF signal amplification in mobile communication devices.
Innovation Solution
The power amplifier circuit design includes a first transistor, a second transistor for bias current supply, and a current output element, with a wiring portion comprising multiple metal layers that overlap specific areas on the semiconductor substrate to enhance thermal coupling between transistors, utilizing a bump and second emitter wiring line for effective heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistors are thermally coupled through a metal electrode layer, then efficiency is improved by preventing junction temperature rise, but thermal coupling strength is insufficient when using bump-based flip-chip mounting due to heat conduction to substrate
Solution Approach 1:
The patent transitions from planar thermal coupling to three-dimensional thermal coupling by extending metal electrode layers vertically above the transistor disposition areas. These elevated metal layers create thermal conduction paths in the vertical dimension, strengthening heat transfer between transistors while isolating them from substrate heat conduction through the bump structure.
Solution Approach 2:
The patent implements nested metal electrode layers where multiple metal layers are stacked vertically, with inner layers positioned within or overlapping outer layers. This nested configuration creates multiple concurrent thermal conduction paths between transistors, significantly enhancing thermal coupling strength without increasing horizontal footprint.
2Temperature
If metal electrode layers are extended to overlap transistor disposition areas, then thermal coupling between transistors is strengthened, but device complexity increases due to additional wiring structures
Solution Approach 1:
The patent designs metal electrode layers that simultaneously serve electrical connection functions and thermal coupling functions. The same metal layers that provide electrical connectivity between circuit nodes are configured to extend and overlap transistor disposition areas, creating thermal conduction paths without requiring separate thermal management structures.
Solution Approach 2:
The patent merges the electrical wiring function and thermal management function into a single integrated metal electrode layer structure. By combining these functions, the patent avoids adding separate thermal coupling components, thereby reducing overall device complexity while achieving enhanced thermal coupling.
3Temperature
If multiple metal layers are stacked to enhance thermal coupling, then heat transfer between transistors is improved, but manufacturing complexity increases due to multi-layer stacking requirements
Solution Approach 1:
The patent incorporates thermal coupling metal layers into the preliminary stages of semiconductor manufacturing, forming these layers as part of the standard multi-layer metal electrode structure during fabrication. By establishing thermal coupling paths during the manufacturing process rather than as a post-processing addition, the patent minimizes additional manufacturing steps and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration strengthens thermal coupling, allowing for better temperature balance and reduced variations in gain, thereby improving the efficiency and stability of the power amplifier circuit.
Implementation Method 1
a wiring portion including a plurality of metal layers that are disposed so as to overlap at least a part of a first disposition area in which the first transistor is disposed and an area between the first disposition area and a second disposition area in which the current output element is disposed... At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from the at least the part of the first disposition area to the second disposition area
Implementation Method 2
In flip-chip connection, a bump is provided in the power amplifier circuit. The semiconductor chip is mounted on the substrate with the bump interposed therebetween. In the case of flip-chip mounting a semiconductor chip including the power amplifier circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-332124, heat conduction to the substrate through a bump affects heat conduction between the transistors through the metal electrode layer
Data Source
AI summary
A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.