MOS Gate Stack With High-k Spacer Structure for Low Leakage
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Solution Overview
Problem
As feature sizes of MOS transistors decrease, the challenge is to enhance capacitance between the gate and channel while maintaining desired physical properties of the gate insulating layer and reducing leakage current, as conventional silicon oxide layers reach physical limits and polysilicon gate electrodes have high resistance.
Innovation Solution
A semiconductor device design incorporating a stacked structure with a metallic gate electrode, a polycrystalline semiconductor electrode, and high-dielectric constant insulating layers, along with spacers on the side walls of the gate electrodes, to optimize the gate-channel capacitance and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a silicon oxide layer is used as a gate insulating layer and its thickness is reduced to increase capacitance, then the capacitance between gate and channel increases, but the leakage current increases and physical properties deteriorate
Solution Approach 1:
The patent uses a composite gate insulating layer structure consisting of a first gate insulating layer (silicon oxide) and a second gate insulating layer (high-dielectric constant material such as hafnium oxide). This composite structure combines the advantages of both materials: the silicon oxide layer provides good interface properties and the high-dielectric constant layer provides high capacitance with thin equivalent oxide thickness, thereby reducing leakage current while maintaining desired capacitance.
Solution Approach 2:
The patent changes the dielectric constant parameter of the gate insulating layer by introducing a high-dielectric constant material layer. This allows achieving the same capacitance with a thicker physical layer, thereby reducing tunneling leakage current while maintaining the required gate-channel capacitance for scaled devices.
2Ease of manufacture
If polysilicon is used as a gate electrode material to simplify fabrication, then the fabrication process is easier, but the resistance is higher
Solution Approach 1:
The patent employs a composite gate electrode structure with a lower gate electrode layer (polysilicon) and an upper gate electrode layer (metal material). The polysilicon layer maintains fabrication compatibility and the metal layer provides low resistance, combining the advantages of both materials to achieve both ease of manufacture and low electrical resistance.
Solution Approach 2:
The gate electrode is divided into multiple layers with different materials - a lower polysilicon layer for fabrication compatibility and an upper metal layer for low resistance. This segmentation allows each layer to perform its optimal function while working together as a unified gate electrode structure.
3Length of moving object
If the gate length is reduced to scale down device features, then the feature size decreases, but the gate-channel capacitance decreases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating layer by using high-dielectric constant materials. This allows achieving the same capacitance value with a reduced gate length, enabling device scaling while maintaining the required gate-channel capacitance for proper transistor operation.
Solution Approach 2:
The composite gate insulating layer structure with high-dielectric constant material enables higher capacitance density, which compensates for the reduced gate length in scaled devices, maintaining the necessary capacitance for proper transistor operation at smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases gate-channel capacitance, reduces leakage current, and improves the operating characteristics of MOS transistors by using a stacked structure with metallic and polycrystalline semiconductor components, enhancing the thin equivalent oxide layer thickness.
Implementation Method 1
research on a high-dielectric layer having a high-dielectric constant is being actively conducted. The high-dielectric layer may reduce a leakage current between the gate electrode and the channel region, while maintaining a thin equivalent oxide layer thickness.
Implementation Method 2
polysilicon, which is mainly used as a gate material, has a higher resistance than most metals. Therefore, the polysilicon gate electrode is replaced with a metal gate electrode
Data Source
AI summary
A semiconductor device includes a first gate electrode structure having a first gate insulating layer on a substrate and a first gate electrode on the first gate insulating layer. A first spacer structure includes a first spacer and a second spacer on side walls of the first gate electrode structure. The first spacer is disposed between the second spacer and the first gate electrode. A source/drain region is disposed on opposite sides of the first gate electrode structure. The first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, and the first spacer is disposed on the side wall of the upper pan of the first gate electrode and is not disposed on the side wall of the lower part of the first gate electrode.