Control Gate Pad Layout for Wider Word Line Etch Window
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Solution Overview
Problem
The small spacing between control gates in memory arrays poses challenges during the formation of word lines, leading to hard mask merge, decreased etch process window, and reduced manufacturing yields due to non-uniform widths and potential leakage paths.
Innovation Solution
A control gate layout with pad regions protruding towards both erase and word lines, increasing the spacing between control gates and preventing hard mask merge, allowing for accurate word line formation with improved etch resiliency and vertical sidewall profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control gates are placed close together to increase memory density, then storage capacity is improved, but hard mask merge occurs during word line formation
Solution Approach 1:
The control gate is divided into multiple segments with pad regions protruding towards adjacent control gates. This segmentation creates isolated etch zones that prevent hard mask merge while maintaining high memory density through efficient space utilization.
Solution Approach 2:
Pad regions are added at specific locations (towards adjacent control gates) rather than uniformly across the entire control gate. This local modification prevents hard mask merge only where needed, maintaining manufacturing precision without adding unnecessary complexity elsewhere.
2Quantity of substance
If control gate spacing is reduced to increase memory density, then storage capacity is improved, but etch process window decreases
Solution Approach 1:
By segmenting the control gate with protruding pad regions, the etch process is divided into manageable zones. This segmentation widens the etch process window even when control gates are closely spaced, enabling high memory density without sacrificing etch process robustness.
Solution Approach 2:
The pad regions act as intermediary structures between adjacent control gates. These intermediaries prevent direct interaction between etch processes of neighboring gates, thereby widening the etch process window and enabling closer gate spacing for increased memory density.
3Quantity of substance
If control gate spacing is reduced to increase memory density, then storage capacity is improved, but non-uniform word line widths occur
Solution Approach 1:
Segmenting the control gate with strategically placed pad regions creates consistent etch conditions across different locations. This ensures uniform word line widths are achieved even when control gates are closely spaced, maintaining manufacturing precision while maximizing memory density.
Solution Approach 2:
Pad regions are positioned at critical locations where width variation would occur without them. This local quality enhancement ensures uniform word line widths specifically at problem areas, maintaining overall manufacturing precision while enabling closer gate spacing for higher memory density.
4Quantity of substance
If control gate spacing is reduced to increase memory density, then storage capacity is improved, but leakage paths between word lines increase
Solution Approach 1:
Segmenting control gates with protruding pad regions creates physical barriers that block leakage current paths. This segmentation prevents harmful electrical interactions between adjacent word lines while maintaining close gate spacing for high memory density.
Solution Approach 2:
Pad regions serve as intermediary barriers between adjacent control gates. These intermediaries physically block leakage current paths that would otherwise exist between closely spaced gates, preventing harmful effects while enabling high memory density through reduced spacing.
Data Source
AI summary
Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.