Vertical Power Gate Layout for Backside Power Delivery
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly as dimensions approach the 10 nanometer node, and traditional power delivery methods lead to increased power network resistance and signal routing issues.
Innovation Solution
The implementation of vertical gate-all-around transistors with backside power delivery, where power is delivered through a vertical keeper or power gate on the backside of the substrate, reducing the need for wide metal wires on the front side and allowing for more efficient power distribution and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional front-side power delivery with wide metal wires is used, then power can be delivered to transistors, but power network resistance increases and signal routing is compromised
Solution Approach 1:
The patent transitions power delivery from the front side (2D planar routing) to the back side of the substrate (3D spatial utilization). By delivering power through the substrate thickness dimension, the invention creates dedicated power pathways that do not compete with front-side signal routing, thereby reducing both power network resistance and signal routing complexity simultaneously
Solution Approach 2:
The patent segments the substrate into functionally distinct regions: the front side for signal processing and the back side for power delivery. This segmentation allows independent optimization of power distribution networks without interfering with signal integrity, resolving the contradiction between power delivery efficiency and signal routing complexity
2Productivity
If multi-gate transistor dimensions are scaled down to maintain density, then device density increases, but mobility improvement and short channel control become difficult to maintain
Solution Approach 1:
The patent employs vertical gate-all-around transistors that utilize the third dimension (vertical depth) for gate control. The gate structure wraps around the channel from all directions, providing enhanced electrostatic control over the channel despite reduced horizontal dimensions. This vertical gating approach maintains short channel control and carrier mobility while enabling continued scaling and increased device density
3Loss of energy
If vertical gate-all-around transistors with backside power delivery are implemented, then power network resistance is reduced and cell height is minimized, but fabrication complexity increases
Solution Approach 1:
The patent divides the fabrication process into distinct front-side and back-side processing sequences. The front side undergoes standard transistor fabrication, while the back side receives dedicated power delivery structure fabrication. This segmentation of manufacturing steps, though increasing overall process complexity, enables the realization of low-resistance power networks and compact cell heights that would be unachievable with conventional monolithic fabrication approaches
Data Source
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AI summary
Structures having vertical keeper or power gate for backside power delivery are described. An integrated circuit structure includes a front-side structure (222) including a device layer (226) having a plurality of fin-based transistors (230), and a plurality of metallization layers (228) above the fin-based transistors of the device layer. A backside structure (224) is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors (234) is between the fin-based transistors of the device layer and the ground metal line of the backside structure.