Split-Gate Trench MOSFET Layout With Uniform Insulation Control
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Solution Overview
Problem
Split gate trench power MOSFETs face challenges with high capacitance between the gate and source electrodes, and the manufacturing process is complex due to non-uniformity in the insulating layer thickness.
Innovation Solution
A trench MOSFET manufacturing method involving the formation of a gate trench, sidewall insulating layer, source electrode, inter-electrode insulating layers, and upper electrodes with specific geometries and layer thicknesses to reduce capacitance and simplify the manufacturing process, including forming a gate insulating layer and second inter-electrode insulating layer to achieve a low capacitance configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a split gate trench power MOSFET structure is used, then breakdown voltage and drain-source resistance are improved, but capacitance between gate and source electrodes increases
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) separated by an insulating layer. This segmentation reduces the capacitance between gate and source by introducing insulating material between the gate segments and the source region, while maintaining the high breakdown voltage characteristics of the trench structure.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the gate electrode and source region. This insulating layer acts as a mediator that reduces the electric field coupling between gate and source, thereby reducing capacitance while allowing the trench structure to maintain its high voltage blocking capability.
2Reliability
If a split gate trench power MOSFET structure is used, then breakdown voltage and drain-source resistance are improved, but manufacturing complexity increases due to non-uniform insulating layer thickness
Solution Approach 1:
A preliminary insulating layer is formed on the sidewalls of the gate trench before the gate electrode is deposited. This preliminary insulating layer serves as a base layer that ensures uniform thickness distribution, making the subsequent gate electrode formation process simpler and more controllable.
Solution Approach 2:
The insulating layer is formed with controlled thickness parameters through a systematic multi-step process involving preliminary layer deposition and selective etching. By controlling the thickness parameters at each stage, uniform insulating layer thickness is achieved, simplifying the overall manufacturing process while maintaining high breakdown voltage performance.
3Object-affected harmful factors
If insulating layer thickness is made non-uniform, then capacitance reduction is achieved, but manufacturing precision deteriorates
Solution Approach 1:
A preliminary insulating layer is deposited uniformly on the gate trench sidewalls before gate electrode formation. This preliminary layer provides a uniform base that ensures consistent insulating thickness throughout the structure, achieving both capacitance reduction and manufacturing precision.
Solution Approach 2:
The insulating layer formation process is divided into controlled steps with specific thickness parameters. By precisely controlling deposition and etching parameters, uniform insulating layer thickness is achieved, simultaneously reducing capacitance and maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the capacitance between the gate and source electrodes, simplifies the manufacturing process, and enhances the efficiency of power semiconductor devices by achieving uniformity in insulating layer thickness, thereby improving device performance.
Implementation Method 1
forming a sidewall insulating layer within the gate trench
Implementation Method 2
forming a source electrode in a lower region of the gate trench by depositing a first conductive layer on the sidewall insulating layer and etching the first conductive layer
Implementation Method 3
forming a gate insulating layer between the sidewall of the gate trench and the first upper electrode
Data Source
AI summary
A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.