FinFET Isolation and Epitaxial Source Drain Structure
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFETs due to issues such as defects, leakage between adjacent fins, and high contact resistance, which affect device performance and cost-effectiveness.
Innovation Solution
A simple and cost-effective process flow is implemented using epitaxially grown source/drain regions with remaining isolation and spacer material between adjacent fins, reducing dislocations and capacitance, and featuring a non-planar surface for increased contact area, thereby improving isolation and AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for FinFETs, then manufacturing complexity is reduced, but device performance deteriorates due to defects and leakage
Solution Approach 1:
The method performs preliminary actions by forming isolation regions and sacrificial fins before forming the main fin structures. This preliminary structuring enables better control during subsequent epitaxial growth and reduces defects in the final FinFET device, improving reliability without significantly increasing overall process complexity
Solution Approach 2:
Sacrificial fins are introduced as intermediary structures that facilitate the formation of isolation regions and guide the epitaxial growth process. These temporary structures enable precise control over fin geometry and isolation, reducing leakage and defects while maintaining manageable fabrication complexity
2Reliability
If isolation material is completely removed between fins, then leakage is reduced, but contact resistance increases
Solution Approach 1:
The isolation material is selectively retained in specific locations - completely removed in channel regions to prevent leakage, but partially maintained in source/drain contact regions to reduce contact resistance. This localized differentiation of isolation material presence optimizes both electrical isolation and contact properties
Solution Approach 2:
The method controls the amount and distribution of isolation material through parameter adjustments in the epitaxial growth process, creating regions with different isolation material thicknesses or complete absence. This parameter control enables simultaneous achievement of low leakage and low contact resistance
3Ease of manufacture
If planar surface is used for source/drain regions, then fabrication is simplified, but contact area is reduced
Solution Approach 1:
The source/drain regions are formed with non-planar, curved surfaces through controlled epitaxial growth rather than flat planar surfaces. This curvature increases the effective contact area with gate and contact structures, improving electrical contact without significantly complicating the fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and leakage between fins, lowers contact resistance, and enhances alternating current performance while maintaining cost-effectiveness in FinFET fabrication.
Implementation Method 1
epitaxially grown source/drain regions
Data Source
AI summary
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.