Inverse Level Shift Circuit Masking for VS Fluctuation Stability
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Solution Overview
Problem
Conventional inverse level shift circuits fail to perform stable operations when the high-side reference potential fluctuates during ON/OFF switching of power switching elements, leading to unbalanced currents and potential destruction due to high currents flowing through transistors.
Innovation Solution
An inverse level shift circuit design that includes a first and second pulse circuit, drive circuits, voltage conversion mask signal generation, mask signal generation, and a mask logical circuit to generate mask signals with higher sensitivity to fluctuations, ensuring stable operation by masking and filtering signals to prevent errors and limit currents through transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inverse level shift circuit is used, then circuit simplicity is maintained, but stable operation cannot be achieved during VS potential fluctuation
Solution Approach 1:
The circuit is divided into multiple functional modules: drive circuits (first and second), voltage conversion mask signal generation circuits (first and second), mask signal generation circuits (first and second), and mask logical circuits (first and second). Each module handles specific aspects of signal processing and mask signal generation, allowing independent optimization and improving overall reliability during VS potential fluctuations.
Solution Approach 2:
Mask signals are generated in advance based on predicted VS potential fluctuations before the actual switching event occurs. The mask signal generation circuits monitor VS potential and prepare mask signals that will be applied during the dV/dt transient period, preventing errors before they can occur.
2Reliability
If mask period is determined by shorter mask signal, then circuit response speed is improved, but error signals are outputted when difference exceeds mask period
Solution Approach 1:
The mask logical circuits perform AND operations between mask signals from both drive circuits, creating a feedback mechanism that dynamically adjusts the effective mask period. This ensures the mask period is sufficient to cover the longer of the two mask signal durations, preventing error signals while maintaining optimal timing.
3Reliability
If signal transmission is performed irrespective of VS potential state, then signal transmission speed is maintained, but high currents destroy the inverse level shift circuit
Solution Approach 1:
Mask signals are generated in advance to counteract the harmful effect of high currents during P potential application. The mask logical circuits apply these mask signals before the dangerous current condition can occur, preventing transistor destruction while allowing normal signal transmission during safe operating conditions.
4Productivity
If transistors are driven during dV/dt transient period, then signal processing capability is maintained, but unbalanced currents produce differences between mask signals
Solution Approach 1:
Different drive circuits are designed with asymmetric characteristics to compensate for the unbalanced currents during dV/dt transient periods. The first and second drive circuits have different parameters optimized for their respective sides, ensuring that mask signals from both sides remain matched despite current imbalances during switching transitions.
Data Source
AI summary
A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals.