3D DRAM Stacked Semiconductor Structures for Higher Memory Density
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Solution Overview
Problem
Current computational devices face challenges in efficiently modeling complex systems due to limitations in computation time and memory density, particularly in dynamic random access memory (DRAM) devices, which hinder further advancements in computational efficiency.
Innovation Solution
The development of three-dimensional (3D) dynamic random access memory (DRAM) with vertically stacked semiconductor structures and innovative cooling systems allows for operation at very low temperatures, enabling reduced semiconductor structure sizes and enhanced performance through increased carrier mobility and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional two-dimensional DRAM structures are used, then manufacturing and operation are simpler, but memory density and computational efficiency are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar DRAM structures to three-dimensional vertically stacked structures. Multiple semiconductor layers are stacked vertically with each layer containing memory cells, allowing significant increase in memory density within the same footprint area. The vertical stacking enables more memory cells to be packed into a smaller volume, directly addressing the limitation of computational efficiency while managing structural complexity through systematic layering.
Solution Approach 2:
The patent implements nested structures where multiple functional layers are integrated vertically. Each semiconductor layer contains memory cells that are nested within the three-dimensional stack, with conductive interconnects routing signals between layers. This nesting approach allows complex functionality to be achieved by organizing simpler repeating units in a hierarchical vertical arrangement, improving memory density without proportionally increasing manufacturing complexity.
2Productivity
If semiconductor structure size is reduced to increase density, then memory density improves, but carrier mobility decreases and leakage increases
Solution Approach 1:
The patent changes the dimensional parameters of the semiconductor structures by transitioning from planar to vertical configurations. The memory cells are arranged in multiple layers stacked vertically, with each layer containing reduced-size transistors and capacitors. This parameter change in spatial arrangement allows smaller individual device sizes while maintaining adequate performance through the three-dimensional configuration, effectively increasing memory density without proportionally degrading carrier mobility or increasing leakage.
Solution Approach 2:
The patent employs composite semiconductor structures with multiple materials stacked vertically. Different semiconductor layers may use varying material compositions optimized for specific functions, such as channel formation, gate insulation, or interconnect formation. This composite approach allows each layer to be optimized for its specific role, maintaining reliable carrier transport and low leakage even as individual device dimensions are reduced to increase overall memory density.
3Reliability
If cooling systems are added to enable low-temperature operation, then carrier mobility and performance improve, but device complexity increases
Solution Approach 1:
The patent merges the cooling function with the existing three-dimensional semiconductor structure. The cooling system is integrated into the vertical stack, utilizing the same interlayer spaces and conductive pathways that are already present in the memory device architecture. This merging approach allows low-temperature operation to be achieved without adding separate, complex cooling infrastructure, as the cooling channels or heat dissipation paths are incorporated into the memory device structure itself.
Solution Approach 2:
The patent designs the three-dimensional semiconductor structure to serve multiple functions simultaneously. The vertical stacking that increases memory density also provides pathways for heat management and cooling fluid flow. The same structural elements that enable high-density storage also facilitate thermal control, allowing the device to operate at optimized temperatures for enhanced carrier mobility without requiring dedicated cooling subsystems that would increase overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved computational efficiency, increased carrier mobility, reduced contact resistance, and enhanced memory density, enabling more compact and efficient DRAM devices that can operate effectively at temperatures as low as −196°C.
Implementation Method 1
an active cooling structure operable to remove heat from an IC die including the semiconductor structures to achieve an operating temperature of the IC die at or below 0° C.
Data Source
AI summary
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.