Bonded Semiconductor Bitline Structure for 3D IC Impedance Reduction
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Solution Overview
Problem
Current 3D integrated circuits (ICs) face challenges with high impedance due to parasitic capacitance, resistance, and inductance, leading to increased access time and costs, particularly with wire bonds and large contact pads, which hinder faster data processing and are costly to manufacture.
Innovation Solution
A bonded semiconductor structure is formed using wafer bonding with a conductive bonding layer and vias to reduce impedance, allowing for faster operation and more efficient data processing by aligning wafers with less expensive equipment and using a conductive bonding layer with a higher melting temperature to minimize voids and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds and large contact pads are used to connect memory and computer chips in 3-D packages, then the chips can be bonded together, but the impedance increases due to parasitic capacitance, resistance, and inductance
Solution Approach 1:
The patent extracts and eliminates the harmful wire bonds and large contact pads from the system. Instead of using traditional wire bonds to connect memory and computer chips, the invention uses through-silicon vias (TSVs) that extend vertically through the substrate, removing the parasitic elements associated with wire bonds and large pads while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from lateral/planar connections to vertical/three-dimensional connections. By using through-silicon vias that extend vertically through the substrate rather than lateral wire bonds, the invention reduces parasitic capacitance and inductance while improving signal integrity and reducing impedance in the interconnect path.
2Ease of manufacture
If large contact pads are used to make alignment easier between chips, then alignment is simplified, but the area occupied increases and yield decreases
Solution Approach 1:
The patent uses thin film conductive layers forming the through-silicon vias instead of large contact pads. These thin film structures provide sufficient electrical connectivity and mechanical support while occupying minimal area, enabling smaller overall device footprint and higher chip yield without compromising alignment capability.
3Loss of time
If memory devices are embedded on the same surface as other devices, then access time is reduced, but mask compatibility problems increase fabrication complexity and cost
Solution Approach 1:
The patent segments the integrated circuit into separate functional layers: memory devices in a first planar layer and logic devices in a second planar layer, with vertical through-silicon vias providing interconnect. This segmentation allows each layer to be fabricated using standard planar processing techniques with compatible masks, while still achieving three-dimensional integration and reduced access time.
4Reliability
If conventional 3-D ICs with wire bonds are used, then chips can be connected, but manufacturing cost increases due to expensive equipment and processes
Solution Approach 1:
The patent replaces the mechanical wire bonding process with a semiconductor fabrication-based approach using through-silicon vias. This substitution eliminates the need for expensive wire bonding equipment and processes, utilizing instead standard semiconductor manufacturing techniques such as photolithography, etching, and deposition, thereby reducing manufacturing cost while maintaining reliable electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bonded semiconductor structure reduces access time and increases data processing speed while being cost-effective and reliable, enabling more efficient data processing in a given amount of time with lower manufacturing costs.
Implementation Method 1
a conductive bonding layer with a higher melting temperature to minimize voids and defects
Implementation Method 2
conductive bonding layer with a higher melting temperature
Data Source
AI summary
The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor.