2T Memory Cell Access Line Plate for 3D Density Scaling
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, leading to inefficiencies in power dissipation and cost per bit.
Innovation Solution
The development of a memory device with two-transistor (2T) memory cells, featuring a charge storage structure and a cross-point gain cell structure, allowing for a smaller footprint, reduced power consumption, and lower costs through the use of a single access and data line for operations, and multiple decks of memory cells stacked vertically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used, then fabrication constraints and physical limitations prevent further size reduction, but storage density cannot be increased
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical stacked architecture. Multiple memory cell decks are stacked vertically with shared bit lines extending through multiple decks, enabling increased storage density without proportionally increasing footprint area or fabrication complexity. This dimensional transition allows continued scaling despite conventional planar fabrication limitations.
2Quantity of substance
If memory cell size is reduced to increase storage density, then storage density improves, but power dissipation increases
Solution Approach 1:
The patent merges multiple memory cell decks vertically with shared bit lines that extend through multiple decks. This consolidation allows multiple memory cells to share common conductive pathways, reducing the total number of independent bit lines required and thereby reducing overall power dissipation despite increased storage density.
3Area of stationary object
If conventional memory cell structures are used, then device area is large, but cost per bit increases
Solution Approach 1:
By stacking multiple memory cell decks vertically rather than expanding horizontally, the patent reduces the footprint area required for a given storage capacity. This vertical integration decreases the device area and associated manufacturing costs per bit while maintaining or increasing storage density.
Data Source
AI summary
Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.