Delay Insertion Gate for CMOS Duty Cycle Distortion Correction
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Solution Overview
Problem
Data-dependent delay errors in CMOS flip-flops lead to significant duty cycle distortions in digital waveforms, affecting the accuracy of sigma-delta digital-to-analog converters, especially at varying temperatures and power supply voltages, making it challenging to maintain precise control over digital waveforms.
Innovation Solution
The implementation of a delay insertion gate with field effect transistors and current mirrors that correct data-dependent switching delays, ensuring that the negative going transition of the Q output is delayed by one gate delay without affecting the positive going transition, thereby reducing duty cycle errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a D-type flip-flop is used to generate digital waveforms, then the circuit is simple and commonly available, but data-dependent delay errors cause significant duty cycle distortions
Solution Approach 1:
The patent introduces an intermediary delay insertion gate between the flip-flop output and the downstream circuit. This gate compensates for the data-dependent delay errors by adding a corrective delay to specific transitions, thereby restoring the duty cycle accuracy without changing the simple flip-flop structure itself
Solution Approach 2:
The patent modifies the timing parameters of the waveform by selectively delaying specific transitions. The delay insertion gate changes the delay parameter for negative-going transitions under specific data conditions, thereby correcting the duty cycle distortion while maintaining the overall circuit simplicity
2Manufacturing precision
If the delay insertion gate delays the negative going transition by one gate delay, then duty cycle errors are reduced, but the circuit complexity increases
Solution Approach 1:
The delay insertion gate implements local quality by applying delay correction only to specific transitions based on data conditions. Rather than uniformly delaying all transitions or redesigning the entire flip-flop, the correction is locally applied where needed, minimizing overall circuit complexity while achieving duty cycle accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces duty cycle errors, improving the accuracy of sigma-delta digital-to-analog converters by correcting data-dependent delay distortions, enhancing the precision and stability of digital waveforms across varying conditions.
Implementation Method 1
A delay insertion gate includes first and second field effect transistors that have gates that are respectively coupled to receive first and second signals
Implementation Method 2
The delay insertion gate may further include a current mirror, which is coupled to the drain terminals of the first and second transistors
Data Source
AI summary
A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.