3D Memory Cell Structure With Gate-All-Around Word Line
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Solution Overview
Problem
The integration degree of two-dimensional memory devices is limited by the area occupied by unit memory cells and requires expensive equipment for fine pattern formation, necessitating the development of three-dimensional memory devices with improved integration.
Innovation Solution
A three-dimensional memory device design featuring a substrate with a lateral active layer, a gate all-around word line, a vertical bit line, and a lateral capacitor, which enhances controllability, reduces word line resistance, and shields interference from neighboring memory cells, while incorporating a high-k dielectric layer and metal-based materials for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory device structure is used, then manufacturing process is simpler, but integration degree is limited
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by vertically stacking multiple active layers (first active layer, second active layer, third active layer) above the substrate. This dimensional change allows memory cells to be arranged in three dimensions, significantly increasing the integration degree without requiring proportionally more complex manufacturing processes.
2Area of stationary object
If fine pattern forming techniques are used to increase integration, then area occupancy is reduced, but equipment cost increases
Solution Approach 1:
Instead of relying solely on reducing the planar area of unit memory cells through fine pattern forming, the patent utilizes the vertical dimension to increase integration. By stacking multiple active layers vertically, the memory device achieves higher integration density without requiring extremely fine lateral patterning, thereby reducing dependence on expensive ultra-fine pattern forming equipment.
Solution Approach 2:
The patent implements a nested structure where multiple active layers are stacked vertically, with each layer containing memory cells that share common bit lines and word lines. This nesting approach allows multiple memory cells to be integrated in a compact vertical arrangement, reducing the lateral area required per memory cell without requiring proportionally finer patterning.
3Quantity of substance
If three-dimensional structure is implemented, then integration degree is improved, but word line resistance increases
Solution Approach 1:
The patent divides the word line into multiple segments corresponding to different active layers (first word line for first active layer, second word line for second active layer, third word line for third active layer). This segmentation allows each word line to be optimized independently, reducing the resistance of individual word lines compared to a single long word line spanning all layers, thereby improving reliability while maintaining high integration.
4Reliability
If gate all-around word line is used, then cell current controllability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements gate all-around word lines that wrap around the active layers in three dimensions, providing electrostatic control from all directions (top, bottom, and sides). This three-dimensional gating structure enhances cell current controllability by fully surrounding the channel region, improving device reliability despite the increased structural complexity.
Data Source
AI summary
A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.