CMOS Analog Switch Body Biasing for Low On-Resistance
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Solution Overview
Problem
Conventional analog switch circuits suffer from body effect-related issues such as increased resistance and leakage current, limiting their dynamic range and efficiency, especially in low-voltage applications, and existing solutions are often complex and costly.
Innovation Solution
The implementation of an adaptable body bias circuit using native transistors with 0V threshold voltages, which responds to terminal voltages to reduce threshold voltage increase and leakage current, thereby minimizing resistance in CMOS switch circuits without requiring additional level-shifting circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional CMOS switch device is used, then the dynamic analog signal range is improved, but body effect causes raised effective threshold voltage and leakage current
Solution Approach 1:
The patent applies dynamic body biasing to the CMOS switch, where the body terminal voltage is dynamically adjusted based on the signal voltage level. This dynamic adjustment compensates for the body effect, maintaining stable threshold voltage across the full dynamic signal range while preserving the enhanced adaptability of the CMOS switch.
Solution Approach 2:
The patent changes the body terminal voltage parameter dynamically to counteract the body effect. By adjusting the body bias voltage in response to signal conditions, the effective threshold voltage is stabilized, eliminating the degradation caused by fixed body bias while maintaining the full dynamic range capability.
2Device complexity
If fixed body bias is applied to MOS transistor, then the structure is simple, but performance is degraded due to raised effective threshold voltage and leakage current
Solution Approach 1:
The patent transitions from fixed body bias to dynamic body biasing, where the body terminal voltage automatically adjusts with signal conditions. This dynamic approach maintains simple device structure while significantly improving switch performance by preventing threshold voltage degradation and reducing leakage current.
Solution Approach 2:
The body biasing mechanism is designed to self-adjust based on the signal voltage level without requiring external control circuitry. The switch device itself generates the appropriate body bias, making the system self-regulating while maintaining structural simplicity and improving performance simultaneously.
3Use of energy by moving object
If gate terminal is biased at ground and body terminal at high voltage supply, then the circuit operates at low voltage, but input signal magnitude is limited by threshold voltage
Solution Approach 1:
The patent dynamically changes the body terminal voltage parameter in response to input signal levels. This allows the switch to operate at low supply voltages while expanding the usable input signal range by compensating for threshold voltage effects, thereby resolving the limitation on signal magnitude.
Solution Approach 2:
The patent applies preliminary body bias adjustment to counteract the threshold voltage limitation before it affects the signal handling capability. By proactively adjusting the body terminal voltage based on expected signal conditions, the switch maintains full dynamic range operation at low voltage levels.
Data Source
AI summary
A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.