Stacked Transistors with Dielectric Insulation for Noise Immunity
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Solution Overview
Problem
Integrated circuit (IC) devices, particularly those with complementary metal-oxide-semiconductor (CMOS) components, face increased sensitivity to voltage variations and signal noise due to shrinking sizes, necessitating improvements in form factor and operational characteristics.
Innovation Solution
The implementation of stacked transistors in a three-dimensional configuration using epitaxial structures at different levels relative to a semiconductor substrate, with dielectric insulation and specific gate and channel materials to enhance electrical insulation and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If IC devices are scaled to smaller sizes, then the form factor and integration density are improved, but the sensitivity to voltage variation and signal noise increases
Solution Approach 1:
The patent transitions from planar transistor arrangements to three-dimensional stacked configurations, utilizing the vertical dimension to increase integration density while maintaining electrical performance. Multiple transistor layers are stacked vertically with gate structures extending through intermediate layers, enabling higher device density without the sensitivity issues that would result from further lateral scaling.
Solution Approach 2:
The patent employs composite material structures including stacked semiconductor layers with different conductivity types (n-type and p-type), dielectric materials for insulation, and conductive materials for interconnects. These composite structures enable independent optimization of electrical characteristics for each layer while maintaining overall device reliability and reducing noise sensitivity through material property differentiation.
2Reliability
If stacked transistor configuration is implemented, then the operational characteristics and noise immunity are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the transistor structure into multiple discrete stacked layers, each with specific functions (e.g., n-type devices, p-type devices, gate structures, dielectric layers). This segmentation allows independent design optimization of each layer while simplifying the overall manufacturing process through modular fabrication steps that can be applied repeatedly to create the stacked configuration.
Data Source
AI summary
Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.