Stacked FET SRAM Layout With Gate Cuts for Cell Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in scaling down SRAM cells while maintaining structural integrity and efficiency, particularly in utilizing stacked field effect transistors (FETs) for smaller devices.
Innovation Solution
The implementation of a semiconductor device with a stacked FET configuration, featuring two top transistors stacked over a single bottom transistor, utilizing full and top gate cut structures to separate device areas, and a bottom gate cut structure to provide the bottom transistor, enabling efficient SRAM cell design with six transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple transistors are stacked vertically to reduce device area, then area efficiency is improved, but manufacturing complexity and precision requirements increase
Solution Approach 1:
The gate structure is segmented into multiple distinct components: full gate structures that wrap around the channel, top gate cut structures that separate adjacent transistors, and bottom gate cut structures that define channel regions. This segmentation allows each gate component to be independently formed and controlled, reducing the overall manufacturing precision requirements while enabling vertical stacking of multiple transistors in a shared channel region.
Solution Approach 2:
The patent transitions from planar transistor arrangements to vertical stacking by utilizing the third dimension (depth). Multiple transistors are stacked above a shared channel region, with gates extending from different vertical levels (full gates wrapping around, top gates from above, bottom gates from below). This dimensional change allows higher transistor density without proportionally increasing manufacturing complexity.
2Productivity
If stacked FET configuration is used to improve SRAM density, then device integration is improved, but structural complexity increases
Solution Approach 1:
The shared channel region serves multiple functions: it acts as the channel for multiple stacked transistors simultaneously, reduces the number of separate channel formations needed, and provides a common foundation for the stacked transistor structure. This multi-functionality improves SRAM density without proportionally increasing structural complexity.
Solution Approach 2:
Adjacent transistors share common structures including the channel region, source/drain regions, and portions of the gate structures. By merging these elements, the patent reduces the total number of discrete components needed, improving integration density while managing structural complexity through shared infrastructure.
Data Source
AI summary
A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.