Subfin Diode Etch Depth Layout for Nanoribbon IC Conductance
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Solution Overview
Problem
In nanoribbon-based transistor technologies, the integration of diodes is challenging due to the limited semiconductor cross-section, which affects electrostatic discharge (ESD) protection and current flow, as conventional processes used for transistors are not optimized for diode formation, leading to increased complexity and cost.
Innovation Solution
The formation of subfin diodes in IC devices with varying etch depths in the subfin region between nanoribbon stacks and a support structure, allowing for improved semiconductor cross-section and conductance while using similar etch processes as for transistors, thereby enhancing diode conductance and current carrying capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional etch processes for transistors are used for diode formation, then process complexity is reduced, but diode conductance and current carrying capability are insufficient
Solution Approach 1:
The patent applies local quality by creating different etch depths in different regions of the subfin structure. Specifically, the etch process removes material to different depths in regions where diodes are formed versus regions where transistors are formed, allowing the subfin to provide adequate cross-sectional area for diode current flow only where needed, while maintaining transistor functionality elsewhere. This resolves the contradiction by locally optimizing diode conductance without increasing overall process complexity.
Solution Approach 2:
The patent utilizes the vertical dimension by varying etch depths through the subfin thickness. Instead of changing lateral dimensions or adding separate diode fabrication steps, the invention creates three-dimensional variation in the subfin structure by etching to different depths, thereby increasing the effective cross-sectional area for current flow in diode regions while maintaining compatibility with planar transistor processes.
Data Source
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Figure 3A~3C
AI summary
Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.