Triple Gate Dual Bit Memory Device for Automotive High Temperature
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Solution Overview
Problem
Current nonvolatile memory devices have low integration density, high resistance, and slow program and erase speeds, and are unable to meet high temperature requirements in automotive applications, particularly in emerging technology nodes like 28 nm to 7 nm metal gate processes.
Innovation Solution
A dual bit memory device with a semiconductor fin and a triple gate structure, comprising a first gate, a second gate, and a third gate positioned over the semiconductor fin, where the lower portion of the third gate is between the first and second gates, allowing for improved data storage and faster operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional floating gate and control gate structure is used, then the device can store data, but the integration density is low and the device size is large
Solution Approach 1:
The patent transitions from a planar two-gate structure to a three-dimensional triple gate structure by adding vertical stacking of gates over the semiconductor fin. This dimensional change allows two bits of data to be stored in a single memory device, effectively doubling the memory density without proportionally increasing the device footprint.
Solution Approach 2:
The patent implements nesting by positioning the lower portion of the third gate between the first and second gates, creating a nested configuration where multiple functional elements are integrated within a compact vertical space. This nested arrangement enables dual-bit storage in a single device structure.
2Speed
If the conventional memory architecture is used, then the device can operate, but the resistance is high and program/erase speed is slow
Solution Approach 1:
The patent applies local quality by introducing a metal gate material specifically in the third gate structure, which provides locally enhanced electrical conductivity. This localized material optimization reduces resistance at critical interfaces and improves overall device speed without requiring complete material replacement throughout the entire device.
Solution Approach 2:
The patent employs composite materials by combining different gate materials (metal gate and polysilicon gate) within the same device structure. Each material is strategically positioned to optimize specific functions: the metal gate provides low resistance for fast operation, while the polysilicon gates provide appropriate threshold voltage control, achieving both high speed and reliability.
3Temperature
If emerging nonvolatile memory structures (MRAM, PCM, RRAM) are used, then faster speed and higher density are achieved, but the high temperature requirements in automotive applications cannot be met
Solution Approach 1:
The patent utilizes parameter changes by adjusting the bandgap and thermal stability characteristics through careful selection of semiconductor fin material composition and gate material properties. This enables the device to maintain stable operation at high temperatures while preserving fast programming and erasing speeds, effectively bridging the gap between temperature reliability and performance speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The triple gate structure increases memory density, reduces device resistance, simplifies fabrication, and meets high temperature requirements, resulting in better memory performance and faster speeds.
Implementation Method 1
A nonvolatile memory device with a triple gate structure i.e., having three gates disposed over the semiconductor fin
Data Source
AI summary
A memory device is provided. The device comprises a semiconductor fin with a first gate and a second gate disposed over the semiconductor fin. A third gate is positioned over the semiconductor fin and a lower portion of the third gate is disposed between the first and second gates.