Epitaxial Source-Drain Regions in LTPS Thin Film Transistors
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Solution Overview
Problem
Conventional methods for forming highly doped source and drain contact regions in thin-film transistors face challenges such as dopant diffusion and non-uniformity, leading to high series resistance and complex activation processes, especially when using low-temperature polysilicon (LTPS) for liquid crystal displays.
Innovation Solution
Employing low-temperature epitaxial growth of highly-doped hydrogenated crystalline silicon (c-Si:H) for the source and drain regions, using a process like plasma-enhanced chemical vapor deposition (PECVD) at temperatures below 450°C, to reduce dopant diffusion and enhance dopant concentration, thereby improving contact resistance and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional high-temperature processing is used to form highly doped source/drain regions, then dopant concentration can be achieved, but dopant diffusion increases and manufacturing complexity increases
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing to low-temperature processing (below 450°C). This parameter change enables highly doped source/drain regions to be formed without excessive dopant diffusion, as the low temperature suppresses thermal diffusion while still allowing dopant incorporation during the epitaxial growth process
Solution Approach 2:
The patent replaces conventional thermal diffusion-based doping with epitaxial growth-based doping. Instead of relying on thermal energy to drive dopant diffusion into the semiconductor lattice, the invention uses epitaxial growth to incorporate dopants directly during crystal formation, achieving high dopant concentration without the need for high-temperature thermal processing
2Manufacturing precision
If low-temperature processing is used, then dopant diffusion is reduced, but dopant concentration and activation become difficult to achieve
Solution Approach 1:
The patent substitutes thermal diffusion mechanisms with epitaxial growth mechanisms. The epitaxial growth process occurs at low temperatures but still achieves high dopant incorporation because dopants are introduced during the crystal growth phase itself, where they are incorporated into the lattice structure as the crystal forms, rather than relying on thermal diffusion after growth
Solution Approach 2:
The patent performs dopant incorporation during the epitaxial growth process itself, before any subsequent thermal activation steps are needed. The dopants are preliminarily incorporated into the crystal structure during growth, and the low-temperature epitaxial process inherently activates the dopants without requiring high-temperature annealing that would cause diffusion
3Ease of manufacture
If conventional doping methods are used, then source/drain regions can be formed, but series resistance remains high and device performance is limited
Solution Approach 1:
The patent uses epitaxial growth to create a replicated crystal structure in the source/drain regions that mirrors the high-quality crystal structure of the channel region. This epitaxial copying process produces highly ordered, low-defect regions with excellent electrical properties, achieving low contact resistance without complex conventional doping and activation sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dopant diffusion and enhances the concentration of dopants in the source and drain regions, leading to improved device performance and stability, enabling higher display resolutions and monolithic integration of driver circuitry in LCDs.
Implementation Method 1
employ a low-temperature epitaxial growth of highly-doped hydrogenated crystalline silicon (c-Si:H) to form at least the highly doped source and drain contact regions
Implementation Method 2
using a process like plasma-enhanced chemical vapor deposition (PECVD) at temperatures below 450°C
Implementation Method 3
reduces dopant diffusion from the source and drain regions
Data Source
AI summary
A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350° C.