Vertical Nanowire Transistor Columns for Compact SRAM Cells
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Solution Overview
Problem
Current memory cell designs, particularly those using finFETs and nanowire transistors, face challenges in achieving compact layouts and finer variations in circuit parameters, leading to inefficiencies in power consumption and operating speed due to larger cell sizes.
Innovation Solution
The implementation of SRAM cells and logic cells using vertical nanowire transistor columns, arranged in configurations such as parallelograms, with intra-cell connectors and conductive pads to optimize layout and connectivity, allowing for smaller and more efficient cell designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If finFETs are used with parallel fin structures, then drive power can be adjusted by changing the number of fins, but cell size becomes large and design granularity is limited
Solution Approach 1:
The patent transitions from planar finFET structures to vertically stacked nanowire transistor columns. By stacking multiple nanowire transistors vertically (e.g., 2-4 transistors per column), the design achieves higher drive power without increasing lateral cell area, as the additional transistor capacity is gained in the vertical dimension rather than by expanding the footprint.
Solution Approach 2:
The patent divides each transistor channel into multiple discrete nanowire segments stacked vertically. Each nanowire acts as an independent channel segment that can be individually controlled by gates, allowing fine-grained adjustment of drive power by enabling or disabling specific nanowire segments while maintaining a compact cell layout.
2Manufacturing precision
If complex reconfiguration of fins is performed to fine tune circuit parameters, then circuit parameters can be optimized, but device complexity increases
Solution Approach 1:
The patent implements dynamically reconfigurable nanowire transistor columns where individual nanowires can be independently enabled or disabled through control gates. This dynamic control allows circuit parameters such as drive strength and threshold voltage to be tuned in real-time without physical reconfiguration, simplifying the design process while maintaining fine-grained adjustment capability.
Solution Approach 2:
The patent enables continuous parameter tuning by varying the number of actively engaged nanowire segments in each column. By changing the operational state (on/off) of individual nanowires or adjusting their individual threshold voltages, circuit parameters can be precisely controlled without requiring complex physical reconfiguration of the fin structures.
3Power
If larger cell sizes are used, then sufficient power can be provided to pull up/down bit line capacitance, but operating speed decreases due to longer bit line lengths
Solution Approach 1:
By stacking nanowire transistors vertically within compact columns, the patent achieves high drive power capability in a small lateral footprint. This allows sufficient current to be provided to charge/discharge bit line capacitance quickly, maintaining high operating speed without requiring expanded cell areas that would lengthen bit line connections.
Data Source
AI summary
A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.