Semiconductor Source/Drain Sidewall Profile Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, reliability, and multi-functionality due to complexities in their fabrication processes, particularly in forming effective source/drain patterns that maintain consistent thickness and reduce defects.
Innovation Solution
The semiconductor device incorporates a channel pattern with sequentially stacked semiconductor patterns, a gate electrode covering the channel, and a gate spacer with an opening exposing the channel, along with source/drain patterns that undergo selective epitaxial growth and reflow processes to achieve specific sidewall profiles, ensuring consistent thickness and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to form source/drain patterns, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to inconsistent thickness and defects
Solution Approach 1:
The gate spacer is formed in advance before the source/drain pattern fabrication. This preliminary structure serves as a template that pre-defines the thickness and shape of the subsequent source/drain patterns through selective epitaxial growth, ensuring consistent thickness without requiring complex real-time control during source/drain formation
Solution Approach 2:
The gate spacer acts as an intermediary structure between the gate electrode and the source/drain patterns. It mediates the thickness control by serving as a physical barrier and growth template, allowing the source/drain material to grow to a precise thickness determined by the spacer dimensions rather than requiring complex deposition control
2Manufacturing precision
If selective epitaxial growth and reflow processes are implemented, then manufacturing precision improves with consistent thickness, but device complexity increases due to additional process steps
Solution Approach 1:
The selective epitaxial growth process utilizes controlled parameters including temperature, pressure, and gas flow rates to precisely control the growth rate and termination points. The reflow process similarly uses controlled heating parameters to achieve uniform rounding. These parameter controls enable high precision thickness uniformity while maintaining process feasibility through standardized semiconductor manufacturing techniques
3Reliability
If gate spacer with opening is used to expose channel, then source/drain contact reliability improves, but device complexity increases due to additional structural elements
Solution Approach 1:
The gate spacer is segmented with an opening that exposes the channel region. This segmentation allows the source/drain patterns to make direct contact with the channel through the opening while the gate electrode remains separated by the spacer segments on either side. The segmented structure enables reliable electrical contact paths while maintaining gate isolation through the remaining spacer portions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of semiconductor devices by reducing process failures and defects, allowing for increased integration and functionality.
Implementation Method 1
performing a selective epitaxial growth process to form the first source/drain pattern having a first sidewall profile
Implementation Method 2
performing a reflow process to change the first sidewall profile of the first source/drain pattern into a second sidewall profile
Data Source
AI summary
A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.