Integrated HVMOS-HVJT Layout for Compact High-Voltage Isolation
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Solution Overview
Problem
Current ultrahigh voltage metal-oxide-semiconductor (MOS) devices face challenges with high process costs and low reliability in extreme environments due to wire bonding, and complexity with metal wires of the back-end-of-line (BEOL) interconnect structure, which limits the number of devices and increases IC chip area.
Innovation Solution
Integration of high voltage metal-oxide-semiconductor (HVMOS) devices with high voltage junction termination (HVJT) devices on a common IC chip area, using a ring-shaped peripheral well to separate and isolate them, allowing for electrical coupling without wire bonding and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for electrical coupling, then reliability is improved, but process cost increases and device complexity increases
Solution Approach 1:
The patent merges the HVMOS device and HVJT device into a single integrated structure on the same IC chip, eliminating the need for separate wire bonding processes. The devices are electrically coupled through integrated interconnect structures formed during the semiconductor fabrication process, thereby reducing both process cost and device complexity while maintaining reliability.
Solution Approach 2:
The patent replaces the mechanical wire bonding system with an integrated electrical interconnect system formed through semiconductor fabrication processes. The interconnect structures are created using standard CMOS fabrication techniques including metal layer deposition and patterning, eliminating the need for post-fabrication wire bonding operations.
2Ease of operation
If metal wires of BEOL interconnect structure are used, then electrical coupling is achieved, but IC chip area increases and device complexity increases
Solution Approach 1:
The patent combines the interconnect structures of the HVMOS device and HVJT device into a shared infrastructure. Common metal layers and interconnect paths are utilized by both devices, reducing the total interconnect area required compared to separate interconnect structures for each device.
Solution Approach 2:
The interconnect structures are designed to serve multiple functions: providing electrical coupling for the HVMOS device, providing electrical coupling for the HVJT device, and enabling signal routing between different circuit blocks. This multi-functionality reduces the overall interconnect area requirement.
3Area of stationary object
If HVMOS devices are integrated with HVJT devices, then IC chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates the HVMOS device and HVJT device fabrication into a unified process flow, allowing both device types to be manufactured simultaneously using the same fabrication steps. This approach leverages the existing precision of standard CMOS fabrication processes while achieving area reduction through integration.
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.