Semiconductor Transistor Layout Beyond Photolithography Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face limitations in reducing the channel length of transistors due to the photolithography method's exposure limits, which restricts the shortening of the distance between source and drain electrodes, thereby hindering the increase of on-state current.
Innovation Solution
A semiconductor device structure with a gate electrode, gate insulating layer, and conductive layers is developed, where one conductive layer overlaps with the insulating layer, and the other does not, allowing for a shorter distance between the source and drain electrodes, and a method involving island-shaped insulating layers and resist masks to form the conductive layers within the exposure limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the photolithography method is used to form patterns, then the manufacturing process is simple and widely applicable, but the minimum pattern size is limited by the exposure limit of the light exposure apparatus, preventing further reduction of channel length
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical patterning by forming the insulating layer with a tapered cross-section. The conductive layers are positioned at different heights on the insulating layer surfaces, enabling sub-lithographic feature sizes through vertical dimension exploitation. This allows channel length reduction beyond photolithography exposure limits while maintaining manufacturing feasibility.
Solution Approach 2:
The insulating layer is formed with a predetermined tapered shape before the conductive layers are deposited. This preliminary structuring creates self-aligned positioning features that guide subsequent conductive layer formation, enabling precise sub-lithographic patterning without requiring additional high-precision lithography steps.
2Productivity
If the distance between source and drain electrodes is reduced to increase on-state current, then the transistor performance improves, but the photolithography exposure limit prevents further shortening of this distance
Solution Approach 1:
The source and drain electrodes are positioned at different vertical heights on the tapered insulating layer, creating a 3D configuration. This vertical separation enables the horizontal distance between electrodes to be reduced below the photolithography exposure limit while maintaining electrical functionality, thereby increasing on-state current.
Solution Approach 2:
The insulating layer exhibits spatially varying properties with its tapered cross-section, creating regions of different heights and slopes. The conductive layers are positioned at specific local regions with optimized heights and positions, enabling enhanced current flow through strategically placed low-resistance contact regions.
Data Source
AI summary
A semiconductor device including a transistor with high on-state current and a fabrication method thereof are provided. A semiconductor device having favorable electrical characteristics and a fabrication method thereof are provided. The semiconductor device includes a substrate, an island-shaped insulating layer over the substrate, and a transistor over the substrate and the insulating layer. The transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, and a pair of conductive layers. One of the pair of the conductive layers includes a region overlapping with the insulating layer, and the other of the pair of the conductive layers includes a region not overlapping with the insulating layer. The level of a top surface of the other of the pair of the conductive layers is lower than the level of a top surface of the one of the pair of the conductive layers. Each of the pair of the conductive layers is in contact with the semiconductor layer. The semiconductor layer includes a region overlapping with the gate electrode through the gate insulating layer.