Shared Fuse Structure for Accurate Status Testing in Semiconductor Arrays
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Solution Overview
Problem
As semiconductor device structures shrink, accurately determining the status of fuse elements becomes challenging due to increased parasitic resistance in shared active regions and gate structures, leading to inaccurate blown resistance values and test results.
Innovation Solution
The semiconductor device structure incorporates a design with shared active regions and gate structures forming fuse elements, where conductive lines are connected to avoid parasitic resistance, allowing for accurate blowing and testing of fuse elements by reducing resistance between active regions and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of memory cell and semiconductor device structure is reduced, then the integration density is improved, but the accuracy of fuse status determination deteriorates due to increased parasitic resistance
Solution Approach 1:
The patent divides the semiconductor device into multiple banks, each with its own dedicated evaluating unit. This segmentation isolates the measurement paths, preventing parasitic resistance from affecting the accuracy of fuse status determination even as device size decreases. Each bank operates independently with dedicated test circuits.
Solution Approach 2:
The patent introduces dummy fuses as intermediary elements in the test circuit. These dummy fuses are used to calibrate and compensate for parasitic resistance effects. By measuring the resistance of dummy fuses under the same conditions as actual fuses, the system can subtract the parasitic component and accurately determine fuse status.
2Area of stationary object
If shared active regions and gate structures are used to reduce device size, then the area is reduced, but parasitic resistance increases affecting testing accuracy
Solution Approach 1:
The patent extracts the parasitic resistance effect from the measurement by using dummy fuses that experience the same parasitic conditions as actual fuses. The parasitic resistance is measured separately through the dummy fuses and then subtracted from the total measured resistance of actual fuses, isolating the true fuse resistance for accurate status determination.
Solution Approach 2:
The patent changes the measurement parameters by performing multiple measurements under different conditions (through dummy fuses and actual fuses) and combining these measurements mathematically. By measuring resistance through different paths and combining the results, the system eliminates the parasitic resistance parameter from the final calculation.
3Quantity of substance
If more fuses are integrated in the same area, then the redundancy capability is improved, but the complexity of fuse status determination increases
Solution Approach 1:
The patent merges multiple fuse arrays into banks that share common evaluating units. Instead of providing separate test circuits for each fuse, multiple fuses within a bank share the same evaluation logic and control circuits. This merging approach allows high integration of fuse elements while keeping the test circuit complexity manageable through resource sharing.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.