NAND Decoder High-Voltage Switch for Bipolar Block Selection
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Solution Overview
Problem
Traditional NAND flash memory designs lack a high voltage switch capable of handling both positive and negative voltage ranges without imposing demanding operational requirements on PMOS transistors, leading to inefficient memory block selection and deselection processes.
Innovation Solution
An integrated circuit high voltage switch comprising a level shifter and a pull-up circuit, where the level shifter receives a decoder signal and outputs a voltage range that includes negative voltages, and the pull-up circuit further widens this range to include both positive and negative voltages, enabling efficient selection and deselection of NAND memory blocks with reduced operational demands on PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a negative level shifter is used to provide negative voltages for block selection, then the voltage range is widened to include negative voltages, but the PMOS transistors have more demanding operational requirements
Solution Approach 1:
A positive level shifter is introduced as an intermediary component between the decoder and the negative level shifter. This positive level shifter converts the decoder signal to a positive voltage range before it reaches the negative level shifter, which then converts it to the required negative voltage range. This two-stage approach allows the PMOS transistors to operate within their safe voltage ranges while still achieving the desired negative voltage output for block selection and deselection.
2Adaptability or versatility
If a positive level shifter followed by a negative level shifter is used, then the voltage range is widened, but the PMOS transistors still have demanding operational requirements
Solution Approach 1:
The invention changes the voltage parameters at different stages of the level shifting process. The positive level shifter outputs a positive voltage that is lower than the maximum positive voltage required by the PMOS transistors, and the negative level shifter then converts this to the required negative voltage range. By carefully controlling the intermediate voltage parameters, the circuit achieves wide voltage range capability while keeping PMOS transistor stress within acceptable limits.
3Device complexity
If traditional x-decoder selector is used without negative voltage capability, then the device complexity is reduced, but the memory block selection and deselection efficiency is reduced
Solution Approach 1:
The level shifting function is segmented into two separate stages: a positive level shifter and a negative level shifter. Each stage performs a specific voltage conversion task, with the positive level shifter handling the initial signal conditioning and the negative level shifter handling the final negative voltage generation. This segmentation allows the circuit to achieve efficient memory block selection and deselection while maintaining a modular and manageable complexity level.
Data Source
AI summary
An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.