Integrated Pixel Memory Array for In-Sensor Computing
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Solution Overview
Problem
Existing hardware-implemented neural networks for image and voice processing are discrete processing units, separated from pixel arrays, requiring data upload for cognitive computing, which is inefficient.
Innovation Solution
An integrated circuit structure with an array of integrated pixel and memory cells, including select transistors, photodiodes, and memory structures (DRAM or ROM), allowing for deep in-sensor, in-memory computing by performing computations directly within the pixel array, eliminating the need for data upload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If discrete processing units are used for hardware-implemented neural networks, then processing speed is improved, but data must be uploaded from pixel arrays to processors, increasing loss of time and reducing productivity
Solution Approach 1:
The patent merges the pixel array and processing unit into a single integrated circuit structure, combining sensing and computing functions in one device. This eliminates the need for data upload between separate components, resolving the time loss while maintaining high processing speed through on-chip neural network operations
Solution Approach 2:
The patent introduces memory cells as an intermediary component between pixel arrays and processing units, enabling data to be stored and processed in-place without physical data movement. This mediator approach eliminates upload time while preserving fast processing capabilities
2Speed
If discrete processing units are used for hardware-implemented neural networks, then processing speed is improved, but the processor is physically separated from the pixel array, increasing device complexity and reducing ease of operation
Solution Approach 1:
The patent combines pixel arrays, memory cells, and processing units into a single integrated circuit structure, reducing system complexity by eliminating separate processing units while maintaining high-speed neural network processing capabilities through on-chip integration
3Productivity
If data is uploaded from pixel arrays to processors for cognitive computing, then computations can be performed, but processing latency increases and productivity decreases
Solution Approach 1:
The patent implements preliminary action by pre-positioning memory cells within the integrated circuit structure to store data in close proximity to processing units. This eliminates the need for data upload and reduces processing latency, thereby increasing computational throughput and productivity
Solution Approach 2:
The patent introduces on-chip memory cells as an intermediary that enables direct data access between sensing and computing elements, eliminating upload delays and reducing processing latency to enhance overall productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient dot product computations within the pixel array, reducing processing latency and enhancing the speed of cognitive computing operations by integrating memory and sensing capabilities.
Implementation Method 1
the photodiode of the specific cell can perform a light sensing process resulting in a second data value being output on the sense node
Data Source
AI summary
Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.