Co-integrating Nanowire Groups with Different Semiconductor Materials
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Solution Overview
Problem
Existing methods for integrating nanowires into semiconductor devices do not allow for the co-integration of different types of semiconductor materials on the same wafer, which is desirable for next-generation devices with small dimensions, and often require a dummy gate for stabilization during thermal annealing and oxide recess.
Innovation Solution
A method involving the formation of fins on a semiconductor-on-insulator substrate, followed by epitaxial growth of different semiconductor materials, such as silicon and silicon germanium, within a dielectric layer to create nanowires with oval cross-sections, which eliminates the need for a separate dummy gate and enables co-integration of n-channel and p-channel devices on the same wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different semiconductor materials are integrated on the same wafer, then device performance and functionality are improved, but manufacturing complexity increases
Solution Approach 1:
The wafer is divided into distinct regions with different semiconductor materials (e.g., silicon regions and III-V material regions) that can be independently processed and then integrated. This segmentation allows each material type to be optimized separately while maintaining overall system functionality, resolving the contradiction between co-integration capability and manufacturing complexity.
Solution Approach 2:
Different semiconductor materials are placed in specific locations on the wafer based on device requirements. Silicon is used in regions requiring mature CMOS compatibility, while III-V materials are placed in regions needing high electron mobility or specific optical properties. This local optimization enables co-integration without requiring uniform processing across the entire wafer.
2Ease of manufacture
If nanowires are formed without dummy gate, then manufacturing steps are reduced, but structural stability during processing deteriorates
Solution Approach 1:
The dummy gate structure is formed early in the fabrication process, before nanowire release, to provide structural support during thermal annealing and oxide recess operations. This preliminary action ensures structural stability during critical processing steps, and the dummy gate can be removed later without affecting nanowire integrity.
Solution Approach 2:
The dummy gate acts as an intermediary structural element that temporarily supports the nanowire structure during processing. It mediates between the need for structural stability and the desire to minimize fabrication steps, providing necessary support only when required and being removable afterward.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the easy co-integration of different semiconductor nanowires on a single wafer, providing enhanced performance by ensuring uniform electrical field distribution and robust integration, while avoiding the need for a separate dummy gate.
Implementation Method 1
forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer
Implementation Method 2
forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins
Data Source
AI summary
A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.