Inverted IC Layout With Lower-Level Routing for Smaller Standard Cells
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, requiring stricter specifications and reliability, particularly in generating and verifying standard cell layout designs to optimize power consumption and speed while maintaining functionality.
Innovation Solution
The integration of a 2-2 AOI circuit design with P-type and N-type metal oxide semiconductor transistors, along with a specific layout design that includes active regions, gate layout patterns, metal over diffusion layout patterns, and conductive features, which provides additional routing resources below upper metallization levels, reducing the need for upper metallization layers and allowing for a smaller pitch and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the integrated circuit is miniaturized to reduce power consumption and increase functionality, then the device size and power consumption are improved, but the design and manufacturing specifications become stricter and reliability challenges increase
Solution Approach 1:
The patent introduces an inverted circuit configuration where circuit elements are positioned below a reference level instead of above it. This dimensional inversion allows for additional routing resources and reduces interference with upper metallization layers, enabling miniaturization while maintaining reliability through improved signal routing and reduced crowding in the standardized direction.
2Use of energy by moving object
If standard cell layout designs are optimized for power consumption and speed, then power efficiency and performance are improved, but the design complexity and verification requirements increase
Solution Approach 1:
The patent inverts the conventional circuit layout by positioning circuit elements below the reference level rather than above it. This inversion provides additional routing resources in the standardized direction, reduces interference with upper metallization layers, and simplifies the routing of power and ground signals, thereby optimizing power consumption without excessively increasing design complexity.
3Ease of operation
If upper metallization layers are used for routing, then connectivity is achieved, but the pitch and area increase
Solution Approach 1:
The patent utilizes the inverted space below the reference level as an additional routing dimension. By positioning circuit elements and routing paths in this inverted region, the design provides additional routing resources without consuming valuable upper metallization layers, thereby maintaining connectivity while reducing the overall pitch and area of the standard cell.
Data Source
AI summary
An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.