Semiconductor Fin Structures with Variable Channel Heights
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Solution Overview
Problem
Current lithographic techniques struggle to achieve multiple fins with varying heights within the limited space of static random access memory (SRAM) cells, compromising either density or performance of multi-gate non-planar FETs, particularly in achieving a beta ratio greater than two between pull-down and pass-gate transistors.
Innovation Solution
The semiconductor structure comprises fins with different channel region heights on the same wafer, achieved by varying the height of semiconductor layers within each fin, allowing for the formation of tri-gate or dual-gate non-planar FETs with distinct effective channel widths, where the overall fin height remains consistent but the semiconductor layer height differs, enabling precise control of the beta ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional lithographic techniques are used to pattern multiple fins in SRAM cells, then fin density can be maintained, but the ability to achieve different effective channel widths (beta ratio > 2) is compromised
Solution Approach 1:
The patent applies local quality by creating fins with different semiconductor layer heights at different locations on the same wafer. The semiconductor layer thickness is varied locally to produce different channel region heights, enabling different effective channel widths for pull-down FETs versus pass-gate FETs without changing the overall fin height or requiring complex lithographic patterning variations.
2Adaptability or versatility
If multiple fins are incorporated to achieve higher beta ratio, then effective channel width increases, but the space required within SRAM cell increases
Solution Approach 1:
The patent changes the parameter of semiconductor layer height to control effective channel width. By varying the semiconductor layer thickness during deposition, the channel region height is adjusted, which directly modifies the effective channel width. This allows achieving beta ratio > 2 without increasing the number of fins or the physical area of the SRAM cell.
3Reliability
If fin height is increased to improve drive current, then short channel effects are suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the fin structure into two distinct parts: the semiconductor layer forming the channel region, and the overlying additional layer(s) completing the fin height. This segmentation allows independent control of channel region height (affecting effective channel width) and overall fin height (affecting depletion and short channel effects), simplifying manufacturing precision requirements.
Data Source
AI summary
Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.