Semiconductor Package Layout for Lower Gate-Loop Magnetic Coupling
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Solution Overview
Problem
Magnetic fields generated by current flow in semiconductor transistors induce unwanted coupling, leading to increased switching losses and reduced efficiency, particularly in high-speed devices like SiC and GaN transistors.
Innovation Solution
A semiconductor package and printed circuit board design that includes specific configurations of external contacts and electrical connectors to reduce or utilize magnetic coupling, such as rearranging pinouts, using magnetic shielding, increasing distances between leads, and altering wire bond configurations to minimize the impact of magnetic fields on the gate control loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the Kelvin emitter configuration is used to reduce switching losses and increase switching speed, then switching efficiency is improved, but magnetic coupling between the source load path and gate control loop increases, leading to higher switching losses
Solution Approach 1:
The patent segments the source connection into two separate paths: a source load path (connecting source to load) and a source sense path (connecting source to gate control loop). This segmentation allows the magnetic field generated by the source load current to be decoupled from the gate control loop, eliminating the harmful magnetic coupling while maintaining the fast switching performance of the Kelvin emitter configuration.
Solution Approach 2:
The patent extracts the sense source/sense emitter connection from the main source/emitter current path. By taking out the sense path and routing it separately through dedicated external contacts and bond wires, the magnetic field interference from the high-current source path is removed from the sensitive gate control loop, resolving the magnetic coupling problem.
2Loss of energy
If external contacts are arranged to reduce magnetic coupling, then switching losses are reduced, but device complexity increases due to additional layout constraints
Solution Approach 1:
The patent applies segmentation by providing separate external contacts for source/emitter and sense source/sense emitter connections. This physical segmentation in the package layout allows independent routing of the source load current and sense current, reducing magnetic coupling while maintaining a systematic and manufacturable design through standardized contact arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces magnetic coupling, thereby enhancing switching speed and efficiency of semiconductor transistors by mitigating the negative effects of magnetic fields on the gate control loop.
Implementation Method 1
magnetic coupling induced by the current flowing through the load path
Data Source
AI summary
A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.