CMOS Analog Switch Control for Wide Input Voltage Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS analog switches face issues with gate insulating film breakdown and leakage currents due to high voltage differences between gate and back gate voltages, limiting their ability to handle input voltages beyond the power supply voltage range.
Innovation Solution
A semiconductor device with a variable voltage circuit that dynamically adjusts the gate and back gate voltages of P channel and N channel transistors based on input voltage, ensuring the voltage difference remains within the gate withstand voltage, preventing film breakdown and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate voltage and back gate voltage are fixed at power supply voltage levels, then the circuit structure is simple, but the voltage difference may exceed the gate withstand voltage when handling high input voltages
Solution Approach 1:
The patent applies dynamics by making the back gate voltage variable rather than fixed. The back gate voltage is dynamically adjusted based on the input voltage level to maintain the voltage difference within the gate withstand voltage limit. This is achieved through a control circuit that monitors the input voltage and adjusts the back gate voltage accordingly, allowing the analog switch to handle a broader voltage range without exceeding the gate insulating film's breakdown voltage.
Solution Approach 2:
The patent changes the parameter of back gate voltage from a fixed value to a variable value that adapts to the input voltage. By varying the back gate voltage parameter in response to input voltage changes, the system maintains the voltage difference across the gate insulating film within safe limits, preventing breakdown while enabling handling of higher input voltages beyond the original power supply voltage range.
2Reliability
If the back gate voltage is set to a voltage other than ground or power supply voltage, then the gate withstand voltage is protected, but leakage current occurs due to forward biasing of the substrate region
Solution Approach 1:
The patent uses dynamics by continuously adjusting the back gate voltage based on the instantaneous input voltage level. The control circuit monitors the input voltage and dynamically sets the back gate voltage to a level that prevents both gate breakdown and excessive leakage current. This dynamic adjustment allows the system to operate reliably across a wide voltage range while minimizing harmful leakage effects.
Solution Approach 2:
The patent implements feedback by using a control circuit that monitors the input voltage and adjusts the back gate voltage accordingly. The control circuit receives feedback about the input voltage level and modifies the back gate voltage to maintain optimal operation, preventing both gate insulating film breakdown and excessive leakage current by keeping the substrate region properly biased.
3Adaptability or versatility
If fixed gate and back gate voltages are used, then the device structure is simple, but the analog switch cannot maintain conducting state for input voltages beyond the power supply voltage range
Solution Approach 1:
The patent applies dynamics by making the gate and back gate voltages variable rather than fixed. The voltage generation circuit dynamically adjusts these voltages based on the input voltage level, allowing the analog switch to maintain its conducting state for input voltages beyond the original power supply voltage range. This dynamic voltage adjustment enables broader adaptability while managing the increased circuit complexity through efficient control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the CMOS analog switch to maintain a conducting state for a broad voltage range without gate insulating film destruction or leakage currents, effectively switching input signals up to the power supply voltage and beyond.
Implementation Method 1
a variable voltage circuit that dynamically adjusts the gate and back gate voltages of P channel and N channel transistors based on input voltage, ensuring the voltage difference remains within the gate withstand voltage
Implementation Method 2
an NMOS transistor is in a conducting state when the gate-source voltage exceeds a positive threshold voltage VthN, but at less than the threshold voltage VthN is in a non-conducting state
Implementation Method 3
If an NMOS transistor and a PMOS transistor are connected in parallel, and if the power supply voltage VDD is applied to the NMOS transistor gate and the ground voltage VSS is applied to the PMOS transistor gate, a conducting state is maintained at any voltage between 0 and VDD
Data Source
AI summary
A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.