4-Terminal JFET Segmented Upper Layer Reduces Gate-Source Capacitance
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Solution Overview
Problem
The existing four-terminal Junction Field Effect Transistors (JFETs) face significant noise amplification due to high capacitance between the gate, gate trace, gate pad, and source, which is not effectively reduced by the current design, leading to suboptimal performance.
Innovation Solution
A reduced capacitance JFET design is implemented by forming a region of the first conduction type in the upper layer to separate it into two sections, placing the gate in one section and the source in another, with a gate pad electrically isolated from the source, and using an insulating material to minimize capacitance between the gate and source, while maintaining low capacitance between the gate and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the gate pad and gate trace are positioned over the source region, then external connection to the gate is achieved, but the capacitance between the gate and source increases significantly
Solution Approach 1:
The upper layer is divided into multiple doped regions including a first doped region beneath the gate, a second doped region beneath the source, and a third doped region between them. This segmentation creates distinct electrical zones that reduce parasitic capacitance while maintaining necessary connections.
Solution Approach 2:
A third doped region is introduced as an intermediary between the gate and source regions. This intermediate region acts as a capacitance-reducing barrier that minimizes the direct capacitive coupling between the gate pad/trace and the source while still allowing both to function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces noise amplification by minimizing the gate-to-source capacitance with minimal adverse effect on the gate-to-substrate capacitance, enhancing the overall performance of the JFET.
Implementation Method 1
The insulating layer 12 may reduce the capacitance between the gate, gate trace, and gate pad 11a-c and the source 13c
Implementation Method 2
The upper layer 15a-c may reduce the capacitance between the gate, gate trace, and gate pad 11a-c and the substrate 14
Data Source
AI summary
A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.