2D Matrix Processor Architecture for Faster Image Convolution
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Solution Overview
Problem
Conventional systems face inefficiencies in performing complex matrix operations due to the need for redundant data storage and retrieval, leading to computational bottlenecks and reduced processing speed, especially in time-sensitive applications like convolutions.
Innovation Solution
An accelerated mathematical engine that reformats data on the fly for efficient matrix operations, utilizing hardware-specific logic to reduce redundant operations and enable parallel processing, thereby minimizing data fetches and enhancing computational throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional scalar machines perform matrix operations using software functions and intermediate storage, then computational flexibility is maintained, but processing speed deteriorates due to redundant data fetches and store operations
Solution Approach 1:
The patent replaces conventional software-based matrix manipulation with dedicated hardware circuitry that performs matrix operations directly. The hardware engine includes specialized units for address generation, data retrieval, and matrix computation that eliminate the need for software interpretation and intermediate storage operations, thereby increasing processing speed while managing computational complexity through architectural specialization
Solution Approach 2:
The patent divides the matrix operation process into distinct functional segments: address generation units that compute memory addresses, data retrieval units that fetch operands, and computation units that perform matrix operations. This segmentation allows each component to be optimized independently and enables parallel execution of multiple operation stages, improving overall processing speed without proportionally increasing complexity
2Loss of time
If data is stored and fetched from registers and cache for each scalar operation, then computational accuracy is maintained, but time consumption increases due to repeated read operations
Solution Approach 1:
The patent implements preliminary address generation and data positioning before the actual matrix computation begins. The address generation units pre-compute memory addresses for all required operands, and data is staged in buffer registers prior to computation. This preliminary preparation eliminates the need for repeated read operations during the computation phase, reducing time consumption while maintaining data accuracy through controlled data staging
Solution Approach 2:
The patent introduces intermediary buffer registers and cache structures that hold data during computation. These intermediary storage elements allow data to be retained without requiring repeated fetches from main memory, and they provide a controlled environment that maintains data integrity and computational accuracy while reducing access time to frequently used operands
3Adaptability or versatility
If convolution operations are converted to matrix-multiply operations with data reformatting, then operational versatility is improved, but data manipulation overhead increases
Solution Approach 1:
The patent designs the hardware engine to perform multiple operations including matrix multiplication, convolution, and other mathematical operations through a unified architecture. The same core computation units can execute different operations by receiving appropriately formatted input data, eliminating the need for separate dedicated hardware for each operation type and reducing overall data manipulation complexity while maintaining operational versatility
Solution Approach 2:
The patent employs parameter-based configuration to switch between different operational modes. By changing control parameters and data formatting requirements rather than reconfiguring the hardware architecture, the system can adapt to different computational tasks. This approach maintains operational versatility while minimizing data manipulation complexity, as the underlying hardware structure remains constant and only the input parameters and data arrangement need to be adjusted
Data Source
AI summary
Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.