Computation Using Non-Contact Making Devices TRIZ Cases

Partial-sum inversion and compressor-tree convolution cut adders, flip-flops, power use, and circuit area in CNN processing.

Scale transformation and S2PM turn private real numbers into matrices, improving secure multiplication speed, accuracy, and data protection.

Bitwise dot-product staging and bit transpose help a double-precision multiplier meet 1400MHz timing and avoid errors in 64-bit by 32-bit operations.

Large N×N CNN filters are split into 3×3 convolutions, cutting memory, multipliers, power use, and FPGA implementation cost.

A digit-difference threshold switches between multiplication algorithms to speed decimal remainder calculation and cut computing cycles.

Separate drivers write transposed and non-transposed weights in opposite directions to raise CIM write and MAC throughput for neural networks.

A Winograd-based neural engine offloads convolutions from the CPU, cutting bandwidth demand and power while improving processing efficiency.

Dedicated Winograd kernel transforms and parallel accumulators shift convolution work off the CPU to cut bandwidth demand and power use.

Adiabatic charge redistribution and a sinusoidal hot clock cut SRAM-C CIM MAC energy, noise, and capacitor area for SWaP-limited designs.

Higher die-to-die bandwidth than external I/O lets this PIM package speed neural network processing while avoiding unnecessary cost and complexity.

A TCAM compute-in-memory array performs MAC operations inside SRAM-based cells to cut processor-memory data transfer and energy use.

A multiplexed shift-and-add multiplier constrains weight bits to cut latency variation, summation hardware, and power in neural calculators.

XNOR-based partial products plus MSB conversion and correction values speed neural-network MAC operations while preserving accuracy.

Bayesian integration of geomechanical priors and seismic machine learning improves reservoir fracture mapping by reducing rare-class over-prediction.

Splitting large bit-width values into smaller components lets limited-width processors handle neural network computing with less overhead.

By replacing repeated divisions with reused inverse multiplication, this case cuts transformer attention scoring time and computational load.

Bit shifting and clipping after MAC output cut convolution data width, lowering memory and circuit area without losing needed accuracy.

Parallel MSB and carry analysis detects overflow early in mixed-width addition, cutting hardware area, delay, and energy use.

Multiple convolution circuits and multiplexers raise NPU resource utilization while cutting circuit area, cost, power, and delay.

On-the-fly data reformatting and synchronized 2D matrix processing cut redundant reads and speed image convolution.

Structured mixed-precision DSP routing cuts AI compute and memory bandwidth without sparsity retraining, with negligible accuracy loss.

A selector-based MAC circuit in PIM switches among multiply, add, and accumulate modes to cut data-transfer bottlenecks in neural computing.

Activation values are split into least and most significant parts so shared multipliers handle outliers with less resource waste.

Streaming FHE logic across segregated RISC cores cuts cache overhead and data-movement energy while making homomorphic encryption more practical.

By breaking convolution transforms into summation operations, this compute circuit cuts matrix multiplications, power use, and processing time.

Fused array instructions cut instruction overhead for matrix and tensor workloads, enabling lower-power local AI processing on integrated circuits.

A unified-ISA array coprocessor accelerates multiply-add array operations locally, cutting power use while protecting data privacy.

Shift-based Gaussian integer reduction replaces complex division with rounded quotients and final reduction to cut cryptographic computation cost.