Array Coprocessor Multiply-Adder for Low-Power AI Operations
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Solution Overview
Problem
Conventional computing devices require significant power and resources to perform array, matrix, and tensor operations, leading to high energy consumption and the need for data transfer to power-hungry datacenters, which compromises data security and privacy.
Innovation Solution
An array coprocessor integrated with a main processor core, sharing a unified Instruction Set Architecture (ISA), enhances energy efficiency and reduces initial hardware costs by performing computations locally on battery-powered devices, using architectures like RVA23 or similar, and integrating via high-speed interconnects or advanced packaging technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processors (CPU/GPU) are used to perform array, matrix, and tensor operations, then computation capability is achieved, but power consumption increases significantly
Solution Approach 1:
The system segments computation tasks by separating general-purpose processing (CPU) from specialized array operations (array coprocessor). The array coprocessor handles specific array, matrix, and tensor operations independently, reducing the energy burden on conventional processors while maintaining overall computation capability.
Solution Approach 2:
An array coprocessor is introduced as an intermediary computing unit between the CPU and memory system. This coprocessor specializes in array operations and communicates with the CPU through a defined interface, enabling energy-efficient processing of parallel computations without requiring full CPU/GPU power consumption.
2Productivity
If data is transferred to datacenters for processing, then AI applications can be executed, but data security and privacy are compromised
Solution Approach 1:
The patent extracts the AI computation capability from centralized datacenters and places it directly on edge devices through the array coprocessor. This extraction enables local processing of sensitive data, eliminating the need to transfer data over networks and thereby preserving data security and privacy while maintaining AI application execution capability.
3Use of energy by moving object
If array coprocessor is integrated with main processor, then energy efficiency improves, but device complexity increases
Solution Approach 1:
The array coprocessor is designed with a universal interface that conforms to the main processor's Instruction Set Architecture (ISA). This universality allows the coprocessor to handle multiple types of array operations (vectors, matrices, tensors) and communicate through standard protocols, reducing integration complexity despite the added functionality.
Solution Approach 2:
The array coprocessor implements a focused subset of computational capabilities specifically optimized for array operations rather than full general-purpose processing. This partial specialization achieves energy efficiency for target workloads while keeping the hardware design simpler than implementing full GPU functionality on every device.
Data Source
AI summary
Systems and methods are directed to accelerating array operations associated with an integrated circuit. The integrated circuit comprises at least one multiply-adder configured to receive a first multiplicand, a second multiplicand, and an addend and to perform an operation to generate an output. The multiply-adder comprises one or more multipliers that multiply the first multiplicand with the second multiplicand to generates a product. The multiply-adder also comprises one or more adders that add the product with the addend to generate a sum. A selector of the multiply-adder then selects the output based on whether the first multiplicand, the second multiplicand, and/or the addend is zero, infinity, non-numeric or finite non-zero.