Dual-Driver Memory Circuit for Bi-Directional CIM Weight Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory circuits face challenges in achieving efficient bi-directional write throughput and multiply-accumulate (MAC) throughput for neural network applications, particularly in computing-in-memory (CIM) operations.
Innovation Solution
The memory circuit is configured with a dual-port memory cell array and separate driver circuits for bi-directional write capability, allowing the first driver circuit to write one set of weight signals in one direction and the second driver circuit to write another set in a different direction, enhancing write throughput and MAC throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single driver circuit is used for memory cell array, then device complexity is reduced, but write throughput and MAC throughput are insufficient for neural network applications
Solution Approach 1:
The memory cell array is divided into two separate banks (first bank and second bank), each served by its own driver circuit. This segmentation allows simultaneous independent write operations to different banks, doubling the effective write throughput without requiring a single complex driver circuit to handle all operations sequentially.
Solution Approach 2:
Each driver circuit is designed to handle multiple functions: writing weight signals to its associated bank, enabling bi-directional write operations, and supporting both transpose and non-transpose modes. This multi-functionality allows the system to achieve high throughput while keeping individual driver circuits relatively simple.
2Productivity
If bi-directional write capability is implemented, then write throughput is improved, but device complexity increases due to separate driver circuits
Solution Approach 1:
The system introduces a bank dimension to the memory architecture, organizing memory cells into first and second banks that can be accessed independently. This dimensional expansion allows parallel write operations in different directions (transpose and non-transpose modes) without increasing the complexity of individual access paths, thereby improving MAC throughput for neural network computations.
3Productivity
If weight signals are written in different directions to memory cell array, then computing-in-memory efficiency is improved, but device complexity increases
Solution Approach 1:
The memory cell array is segmented into two banks with dedicated driver circuits, allowing weight signals to be written in different directions (transpose mode to first bank, non-transpose mode to second bank) simultaneously. This segmentation enables efficient computing-in-memory operations by matching data flow patterns with appropriate storage orientations without requiring a single complex driver to manage all write directions.
Data Source
AI summary
A memory circuit includes a memory cell array, a multiply-accumulate (MAC) circuit, a first and second driver circuit. The memory cell array is configured to store a first or second set of weight signals. The second set of weight signals is transposed with respect to the first set of weight signals. The MAC circuit is configured to generate a first set of data in response to a set of input data and one of the first or second set of weight signals. The first driver circuit is configured to write the second set of weight signals to the memory cell array in response to being enabled by a first enable signal. The second driver circuit is configured to write the first set of weight signals to the memory cell array in response to being enabled by a second enable signal inverted from the first enable signal.