Streaming RISC Architecture for Cache-Efficient FHE Execution
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Solution Overview
Problem
Conventional processor architectures, including RISC and GPU designs, are inefficient for handling large amounts of data movement due to cache overhead and energy consumption, which is exacerbated by multi-core designs, and Fully Homomorphic Encryption (FHE) algorithms require significant computing resources that are not readily available with these architectures.
Innovation Solution
A reduced instruction set computer processor architecture is configured to operate in a streaming mode, utilizing RISC processors with segregated primary and secondary cores, where data streams directly between arithmetic logic units, reducing the need for cache operations and enabling efficient execution of FHE algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional RISC processors use multiple levels of memory caches to execute large code bases, then code execution speed is improved, but data movement efficiency deteriorates due to cache overhead and energy consumption
Solution Approach 1:
The processor architecture is segmented into separate control-centric cores for instruction execution and data-centric cores for data movement operations. This segmentation allows each core type to be optimized for its specific function, eliminating the need for all cores to maintain complex cache hierarchies, thereby reducing energy consumption while maintaining code execution speed.
Solution Approach 2:
The data movement functionality is extracted from the control-centric processor cores and assigned to dedicated data-centric cores. This extraction removes the cache overhead burden from the instruction execution path, allowing control-centric cores to execute code efficiently while data-centric cores handle data movement with minimal energy consumption.
2Power
If multi-core processor designs are used to increase computing power, then processing capability is improved, but cache overhead and device complexity increase
Solution Approach 1:
The multi-core system is segmented into two distinct types of cores with specialized functions. This segmentation simplifies the overall device complexity by allowing each core type to have a simpler, type-specific cache architecture rather than requiring all cores to support a complex unified cache hierarchy.
Solution Approach 2:
Data movement operations are extracted from the control-centric cores and handled by dedicated data-centric cores. This extraction reduces the cache coherence requirements across all cores, simplifying the cache hierarchy while maintaining high computing power through the specialized data-centric processing.
3Reliability
If Fully Homomorphic Encryption algorithms are executed on conventional processor architectures, then encryption processing is achieved, but computing resource requirements are excessive
Solution Approach 1:
The FHE algorithm execution is segmented into control-centric core tasks for algorithm control and data-centric core tasks for intensive data processing. This segmentation allows the system to achieve reliable encryption processing with reduced overall computing resource requirements by utilizing the specialized capabilities of each core type.
Solution Approach 2:
The computationally intensive data processing portions of FHE algorithms are extracted from the control-centric cores and assigned to data-centric cores. This extraction reduces the resource burden on control-centric cores while maintaining the security and reliability of the encryption processing.
Data Source
AI summary
Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.