Double-Precision Multiplier with Bit Transpose for 1400MHz Timing
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Solution Overview
Problem
Conventional components in integrated circuits fail to meet timing requirements for high-speed multiplication operations required for ultra-high definition video processing, particularly at 64bit x 32bit multiplication at 1400MHz, and result in inconclusive errors during complex operations.
Innovation Solution
A method and system for performing double-precision high-speed arithmetic operations involving register circuits, logical circuits, transpose circuits, and computation circuits to arrange and process input data through bitwise AND operations, row-wise arrangement, transpose operations, and additional arithmetic operations to generate final output data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional multiplication components are used in integrated circuits, then device complexity is reduced, but timing requirements for high-speed multiplication operations (64bit x 32bit at 1400MHz) cannot be met
Solution Approach 1:
The multiplication operation is divided into multiple stages: first logical operation to generate dot products, arrangement of dot products in row-wise manner, first arithmetic operation on row-wise arranged dot products, transpose operation on bit elements, and second arithmetic operation on transposed bit elements. This segmentation allows each stage to be optimized independently to meet timing requirements at 1400MHz
Solution Approach 2:
The patent introduces a transpose operation that rearranges bit elements from column-wise to row-wise arrangement, adding a dimensional transformation step. This allows optimization of carry propagation paths and enables parallel processing in subsequent stages, achieving high-speed operation despite increased circuit complexity
2Reliability
If conventional multiplication components are used, then ease of manufacture is improved, but inconclusive errors occur during complex multiplication operations
Solution Approach 1:
By dividing the multiplication into distinct logical operations (logical operation, first arithmetic operation, transpose operation, second arithmetic operation), each stage can be verified and tested independently, reducing propagation of errors and improving overall reliability of the multiplication operation
Solution Approach 2:
The transpose operation serves as an intermediary step that transforms the arrangement of bit elements between the first and second arithmetic operations. This intermediate transformation ensures proper alignment of operands and eliminates inconclusive errors by establishing deterministic data flow between stages
3Loss of time
If conventional arithmetic operation components are used, then device complexity is reduced, but latency in high-speed multiplication operations increases
Solution Approach 1:
The first logical operation generates all dot products in advance before the first arithmetic operation begins. The row-wise arrangement of dot products is prepared beforehand to optimize subsequent addition operations, reducing critical path latency in the multiplication pipeline
Solution Approach 2:
The transpose operation dynamically reconfigures the arrangement of bit elements based on the results of the first arithmetic operation. This dynamic reorganization optimizes the data flow for the second arithmetic operation, minimizing latency despite the additional transformation step
Data Source
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AI summary
A method for performing a double precision high-speed arithmetic operation includes receiving first input data and second input data, generating first output data by performing a first logical operation on each of the first input data and the second input data, arranging a plurality of dot products in a row-wise manner, generating a second output data by performing a first arithmetic operation on the dot products, performing a transpose operation on a plurality of bit elements of the second output data by arranging least significant bits of the plurality of bit elements and the most significant bits in successive rows, and generating final output data by performing a second arithmetic operation on the transposed bit elements.