Multiplexed Shift-and-Add Multiplier for Low-Latency Neural Weights
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing shift-and-add multipliers for neural networks face complexity and latency issues when performing multiplication operations with different multiplicative values, leading to inefficient hardware implementation and management of varying time latencies.
Innovation Solution
A multiplexed shift-and-add multiplier with a set of shift units, multiplexing units, and summation units, controlled by a control unit to minimize latency differences by constraining multiplicative values to have at most K non-zero bits, reducing the number of summation units and optimizing hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional shift-and-add multipliers are used for all multiplication operations in neural networks, then multiplication by different weight values is possible, but hardware complexity becomes too high
Solution Approach 1:
The patent applies universality by designing a single multiplier circuit that can handle multiple weight values through parameter configuration. The multiplier uses a configurable number of shift units (K) and accepts different weight values as inputs, allowing the same hardware structure to perform multiplication by various constants without requiring separate dedicated circuits for each weight value.
2Device complexity
If multi-constant multipliers are used to mutualize computational resources, then hardware complexity is reduced, but time latency becomes difficult to manage
Solution Approach 1:
The patent applies segmentation by dividing the multiplication operation into multiple parallel shift units. Each shift unit processes a portion of the computation independently, and their results are summed to produce the final product. This parallel segmented architecture reduces the critical path delay compared to sequential approaches, thereby managing and reducing time latency while maintaining hardware efficiency.
3Device complexity
If the number of summation units is reduced to simplify hardware, then device complexity decreases, but the ability to handle different multiplicative values is limited
Solution Approach 1:
The patent applies dynamics by making the number of active shift units configurable based on the specific weight value being used. The system dynamically adjusts which shift units are activated and how many summation operations are performed, allowing the same hardware with a fixed small number of summation units to adaptively handle different multiplicative values with varying complexity requirements.
Data Source
AI summary
A shift-and-add multiplier able to perform multiplication operations by multiplicative values, configured to receive as input a binary value and to deliver the product of the value and of a respective multiplicative value. It includes a set of shift units, each connected to the input and configured to perform a bit shift of the value received at the input, varying from one shift unit to another; and a set of summation units, configured to sum the outputs of the shift units. It includes a set of multiplexing unit(s) connected between the set of shift units and the set of summation unit(s), and a control unit configured to control the set of multiplexing unit(s) to select respective outputs of the shift units according to the multiplicative value and to deliver them to the set of summation unit(s).