Convolution MAC Post-Processing for Reduced Bit-Width Output
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Solution Overview
Problem
Current convolution operation devices face high circuit implementation costs due to the need for larger input bit widths to process large operation results from multiply-accumulate circuits, leading to increased memory and circuit area requirements.
Innovation Solution
A convolution operation device with a post-processing circuit that performs bit shifts and clipping operations on initial operation data using pre-configured shift values, reducing the bit width of operation data and minimizing circuit area and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processing circuit supports a larger input bit width to completely receive and process the operation result from the MAC circuit, then the processing completeness is improved, but the overall costs of the processing circuit are significantly increased
Solution Approach 1:
The patent performs bit truncation and clipping operations on the operation result before it is fully processed by the processing circuit. By preliminarily reducing the bit width of the operation result data, the circuit only needs to handle reduced-precision data, significantly lowering the input bit width requirement and overall circuit costs while maintaining sufficient processing completeness for the application
Solution Approach 2:
The patent changes the parameter of data precision by truncating the bit width of the operation result from the full MAC output precision to a reduced precision level. This parameter change allows the processing circuit to operate with lower bit width requirements, reducing circuit complexity and implementation costs while maintaining acceptable processing accuracy
2Measurement precision
If the processing circuit uses a larger input bit width to process the operation result, then the data accuracy is improved, but the memory and circuit area requirements are increased
Solution Approach 1:
The patent performs preliminary bit truncation and clipping operations to reduce the operation result to an optimized bit width that balances accuracy and area requirements. This preliminary processing ensures that the data maintains sufficient accuracy for the application while the reduced bit width allows the processing circuit to be implemented with smaller area
Solution Approach 2:
The patent optimizes the data precision parameter by reducing the bit width of the operation result to a level that provides sufficient accuracy for the application. This parameter optimization enables the processing circuit to achieve the required measurement precision with a smaller circuit area, resolving the trade-off between accuracy and area
Data Source
AI summary
A convolution operation device includes a multiply-accumulate (MAC) circuit and a post-processing circuit. The MAC circuit performs a convolution operation according to first feature data and a weight coefficient to generate initial operation data and generates a completion signal. The post-processing circuit obtains a first shift value from a memory according to the completion signal, performs a bit shift on the initial operation data according to the first shift value to generate shifted operation data, and performs a first clipping operation on the shifted operation data according to a predetermined value range to generate first operation data, wherein the number of bits of the first operation data is less than the number of bits of the initial operation data.