XNOR Multiplier-Accumulator With MSB Conversion for Accurate MAC
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Solution Overview
Problem
Existing vector matrix multiplication operations in neural networks, such as MAC operations, are limited by their performance, which affects the overall processing efficiency of neural networks, particularly in machine learning and authentication tasks.
Innovation Solution
A multiplier-accumulator circuit utilizing XNOR gates with MSB conversion to 2's complement and correction values for input and weight sequences, enabling efficient MAC operations by compensating for errors in the new number system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MAC operations are used in neural networks, then the processing can be performed with standard circuitry, but the performance and computational efficiency are limited
Solution Approach 1:
The patent changes the numerical representation parameter from conventional binary to a new number system where the MSB has a negative weight. This parameter change enables the use of XNOR gates instead of traditional multipliers, significantly improving computational efficiency while maintaining accuracy through the specific encoding and correction mechanisms described in the patent
Solution Approach 2:
The patent substitutes complex multiplication operations with simpler XNOR gate operations. By replacing the traditional mechanical/computational multiplication process with logical XNOR operations followed by accumulation, the system achieves higher performance while using simpler circuitry
2Speed
If a new number system with MSB conversion is used to improve MAC operation efficiency, then computational speed increases, but errors may occur due to the conversion from 2's complement
Solution Approach 1:
The patent applies preliminary anti-action by introducing correction values that compensate for errors before they affect the final result. The correction mechanism is built into the computation process, adding or subtracting specific values based on the MSB conversion to ensure accuracy is maintained despite the number system transformation
Solution Approach 2:
The patent implements feedback through the correction value mechanism, where the system monitors the computational process and applies corrective actions based on the specific patterns generated by MSB conversion. This feedback loop ensures that any potential errors from the number system conversion are automatically corrected
Data Source
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AI summary
A multiplier-accumulator includes: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is converted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed.