Winograd Neural Processor Circuit for Lower-Power Convolutions
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Solution Overview
Problem
Existing neural networks rely heavily on central processing units (CPUs) for convolutions, leading to significant CPU bandwidth consumption and increased power consumption.
Innovation Solution
A neural processor circuit with a data storage device and neural engine circuit that performs convolutions using a Winograd transform, incorporating multipliers, accumulators, and a kernel transformation circuit to generate intermediate kernel parameters, allowing parallel processing of convolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If neural networks use CPU for convolution operations, then computational flexibility is maintained, but CPU bandwidth consumption increases and power consumption increases
Solution Approach 1:
The patent divides the neural network processing into two distinct parts: a neural processing unit (NPU) dedicated to convolution operations and a CPU for control and non-convolution tasks. This segmentation allows the energy-intensive convolution operations to be offloaded to the NPU, reducing CPU bandwidth consumption and overall power consumption while maintaining computational flexibility through the CPU's ability to handle diverse workloads.
Solution Approach 2:
The patent introduces a neural processing unit as an intermediary component between the CPU and the convolution operations. This NPU acts as a specialized co-processor that handles convolution computations, freeing the CPU from these specific tasks and reducing its bandwidth consumption while maintaining system flexibility through the CPU-NPU interface.
2Adaptability or versatility
If neural networks use CPU for convolution operations, then general-purpose computing is maintained, but processing speed decreases
Solution Approach 1:
The patent segments computing tasks into general-purpose CPU operations and specialized convolution operations handled by the NPU. This segmentation enables parallel processing where the NPU accelerates convolution operations at higher speed while the CPU maintains general-purpose computing capabilities, thus improving overall processing speed without sacrificing adaptability.
Solution Approach 2:
The patent replaces the general-purpose CPU execution mechanism with a specialized NPU architecture optimized for convolution operations. This substitution introduces a dedicated hardware structure with specialized units (convolution units, activation units, pooling units) that can perform convolution operations more efficiently and at higher speed than general-purpose CPU instructions.
3Ease of manufacture
If traditional convolution methods are used, then implementation simplicity is maintained, but computational efficiency decreases
Solution Approach 1:
The patent changes the computational parameters and organization of convolution operations by implementing them in a specialized NPU architecture with dedicated convolution units, activation units, and pooling units. This parameter change in the computational approach—moving from general-purpose sequential processing to specialized parallel processing—dramatically improves computational efficiency while the modular design maintains implementation simplicity through clear functional separation.
Data Source
AI summary
Embodiments relate to a neural processor circuit including a data storage device and a neural engine circuit. An input transformation circuit can generate, at a first time instance, a first set of intermediate input parameters corresponding to a first subsequence of input parameters; generate, at the first time instance, a second set of intermediate input parameters corresponding to a second subsequence of input parameters; and generate, at a second time instance, a third set of intermediate input parameters corresponding to a third subsequence of input parameters. A kernel transformation circuit of the neural engine circuit generates a number of intermediate kernel parameters, which are used for a first pair of convolutions based on the first set of intermediate input parameters, a second pair of convolutions based on the second set of intermediate input parameters, and a third pair of convolutions based on the third set of intermediate input parameters.