Reconfigurable MAC Circuit for Processing-in-Memory Neural Computing
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Solution Overview
Problem
The integration of memory and processor in a single semiconductor chip, known as a PIM device, is necessary to improve data processing speed in neural networks due to the limitations of data communication between separate memory and processor systems, which degrade the performance of artificial intelligence systems.
Innovation Solution
A multiple operation circuit comprising a multiplier, an adder, a latch circuit, and selectors, which can perform various arithmetic operations in different modes, including MAC operations, element-wise operations, and accumulating calculations, integrated within a PIM device to enhance data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory and processor are separated, then device complexity is reduced and ease of manufacture is improved, but data processing speed and AI performance are degraded due to communication limitations
Solution Approach 1:
The patent merges the memory and processor into a single integrated device (PIM device), allowing data to be processed directly at the memory location without requiring data transfer between separate components. This integration eliminates communication bottlenecks and significantly improves data processing speed for neural network operations.
Solution Approach 2:
The multiple operation circuit is designed to perform various arithmetic operations including MAC operations, element-wise operations, and accumulating calculations within the same integrated structure. This multi-functionality allows the device to handle different neural network computation types without requiring separate specialized hardware, maintaining versatility while improving speed.
2Productivity
If multiple operation modes are integrated in a single circuit, then productivity and processing efficiency are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The multiple operation circuit implements multiple operation modes (MAC operations, element-wise operations, accumulating calculations) within a single unified circuit structure. This multi-functional design enables the circuit to perform various neural network computations without requiring separate dedicated hardware for each operation type, thereby improving processing efficiency while maintaining reasonable manufacturing complexity.
Solution Approach 2:
The circuit incorporates selectors that can dynamically switch between different operation modes based on the computational requirements. This dynamic reconfigurability allows the same physical circuit to adapt its functionality, maximizing productivity by handling different operation types through a single flexible structure rather than requiring multiple fixed-function circuits.
Data Source
AI summary
A multiple operation circuit includes a multiplier, an adder, a latch circuit, and a plurality of selectors. The multiplier performs a multiplying calculation of first input data and second input data to generate and output multiplication result data. The adder performs an adding calculation of third input data and fourth input data to generate and output addition result data. The latch circuit latches fifth input data input to an input terminal of the latch circuit to generate and output feedback data. The plurality of selectors change transmission paths of first result data, the first input data, the second input data, the multiplication result data, and the addition result data according to a first operation mode, a second operation mode, or a third operation mode.