CNN Convolution Partial-Sum Inversion for Lower-Power Circuits
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Solution Overview
Problem
Existing convolution neural network (CNN) implementations face inefficiencies in energy consumption due to separate multiplication and addition operations, which do not optimize energy efficiency.
Innovation Solution
A method involving partial sum expansion, inversion, and bit manipulation followed by a compressor tree circuit to efficiently perform multiplication and addition operations in CNNs, utilizing a compressor tree circuit with optimized compressor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional multiplication and addition operations are used in convolution neural networks, then computational accuracy is maintained, but energy consumption and power usage increase significantly
Solution Approach 1:
The patent segments the multiplication operation into obtaining partial sums by multiplying input feature values by individual bits of weight values. This segmentation allows for optimized processing of each partial sum through inversion and compression operations, reducing overall energy consumption while maintaining computational accuracy.
Solution Approach 2:
The patent applies inversion by inverting the expanded first partial sums to convert them into inverted first partial sums. This inversion technique, combined with subsequent compression operations, reduces the number of adders required and lowers power consumption while preserving the computational result.
2Loss of energy
If the number of adders and flip-flops is reduced to lower power consumption, then energy efficiency improves, but the complexity of the computational architecture increases
Solution Approach 1:
The patent performs preliminary actions by expanding the first partial sums with zero sequences before inversion, and by pre-processing the weight values into sign bits and magnitude bits. These preliminary steps simplify subsequent operations and reduce the number of adders needed, lowering power consumption despite the initial expansion step.
Solution Approach 2:
The patent changes parameters by representing weight values in a specialized format with separate sign bits and magnitude bits, and by transforming partial sums through inversion operations. These parameter changes enable the use of compression techniques that reduce the number of adders and flip-flops required, decreasing power consumption.
3Area of stationary object
If compression techniques are applied to reduce the number of adders, then area usage decreases, but the complexity of the compression circuit increases
Solution Approach 1:
The patent implements a compressor tree structure where compression operations are nested in a hierarchical manner. First compressors process groups of partial sums, and second compressors process the outputs of the first compressors. This nested arrangement efficiently reduces the number of adders required while organizing circuit complexity in a manageable hierarchical structure.
Solution Approach 2:
The patent transitions from a conventional addition-based approach to a compression-based approach that operates in a different computational dimension. By using compression trees that reduce multiple inputs to fewer outputs through specialized compression logic, the circuit area is reduced while the complexity is managed through systematic organization of compression stages.
Data Source
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AI summary
A convolution processing method performed by at least one processor included in an electronic apparatus, including: obtaining a plurality of partial sums by multiplying a plurality of input feature values in a binary form by a plurality of weight values in the binary form; inverting a plurality of first partial sums from among the plurality of partial sums, wherein the plurality of first partial sums correspond to results obtained by multiplying each input feature value from among the plurality of input feature values by a sign bit corresponding to each weight value from among the plurality of weight values; and obtaining an output feature value based on the inverted first partial sums, additional bits, and remaining partial sums other than the inverted first partial sums.