2D Memory Cell Etching for Protected BEOL 1T-1C Integration
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Solution Overview
Problem
Existing semiconductor technologies face challenges in creating high-density memory storage due to limitations in manufacturing processes that damage thin 2D layers, making precise etching and integration of components difficult.
Innovation Solution
A manufacturing process involving a combination of dry and wet etching techniques is used to create precise cavities in the dielectric and cap layers, allowing for the formation of 2D transistors with sources and drains that can be integrated with capacitors, forming a 1T-1C memory cell structure, utilizing materials like transition metal dichalcogenides and high-quality insulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used to create high-density memory storage, then manufacturing simplicity is maintained, but the thin 2D layers are damaged and etching precision is insufficient
Solution Approach 1:
The etching process is segmented into two distinct stages: first a dry etch process is applied to create initial cavities in the dielectric layer, then a wet etch process is used to complete the cavities through the cap layer to the 2D layer. This segmentation allows each process to be optimized for its specific function, achieving precise etching without damaging the thin 2D layers.
Solution Approach 2:
The cap layer serves as an intermediary protective layer between the dielectric layer and the thin 2D layer. During the dry etching process, the cap layer protects the 2D layer from damage while allowing precise cavity formation in the dielectric layer. The cap layer is selectively removed only where needed to expose the 2D layer for source and drain formation.
2Adaptability or versatility
If higher memory density is achieved through integration, then memory functionality is enhanced, but the integration difficulty increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked memory cells. By stacking multiple memory cells vertically, the design achieves higher memory density and enhanced functionality without proportionally increasing lateral device complexity. The vertical stacking allows multiple capacitors and transistors to be integrated in a compact footprint.
Solution Approach 2:
The memory cell structure employs nested configuration where capacitors are integrated within or adjacent to transistor structures. The source and drain regions are formed in cavities that are nested within the dielectric and cap layers, and the capacitor structures are nested within the overall memory cell architecture, achieving high integration without excessive complexity.
3Area of moving object
If thin 2D layers are used to reduce device size, then device footprint is reduced, but the layers become vulnerable to manufacturing damage
Solution Approach 1:
The cap layer is deposited beforehand to cover and protect the thin 2D layer during subsequent manufacturing processes. This protective cap layer cushions the 2D layer against mechanical damage during etching and material deposition processes. The cap layer is only removed in specific regions where source and drain contact with the 2D layer is required, maintaining both device miniaturization and layer integrity.
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.