2D Scan Compression Layout for Low-Power ATPG
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Solution Overview
Problem
Current power management during Automatic Test Pattern Generation (ATPG) in integrated circuits is inefficient, leading to excessive power dissipation and IR drop issues due to high switching activity, which is not effectively addressed by post-processing techniques like clock gating that often result in conflicts and reduced power target achievement.
Innovation Solution
The implementation of physically-aware systems and methods that partition the integrated circuit into regions with grouped scan channels, using a processor to enable and disable clock gates selectively across scan flops, thereby optimizing power dissipation by controlling clock signals based on the physical location of scan channels and toggle rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based manufacturing tests are applied to low power designs, then fault detection capability is improved, but power dissipation increases excessively causing voltage droop
Solution Approach 1:
The patent applies preliminary action by determining care bits for scan flops before ATPG generates test patterns. The system identifies which scan flops need to maintain their values during capture and pre-calculates the care bit patterns. This allows the ATPG process to generate power-aware test patterns that inherently satisfy both fault detection requirements and power constraints, rather than attempting to modify patterns after generation.
Solution Approach 2:
The patent changes parameters by integrating power constraints directly into the ATPG pattern generation process. The system modifies the ATPG workflow to accept power targets and toggle rate constraints as input parameters, then generates test patterns that satisfy these constraints. This transforms the approach from post-processing power management to constraint-driven pattern generation, fundamentally changing how test patterns are created.
2Use of energy by moving object
If clock gating is applied after ATPG generates test patterns, then power dissipation is reduced, but conflict with existing care bits reduces power target achievement
Solution Approach 1:
The patent applies preliminary action by determining care bits for scan flops before ATPG generates test patterns. The system identifies which scan flops need to maintain their values during capture and pre-calculates the care bit patterns. This allows the ATPG process to generate power-aware test patterns that inherently satisfy both fault detection requirements and power constraints, rather than attempting to modify patterns after generation.
Solution Approach 2:
The patent inverts the conventional approach by applying clock gating considerations during pattern generation rather than as a post-processing step. Instead of generating patterns first and then attempting to gate clocks (which creates conflicts), the system generates patterns with clock gating constraints already embedded, eliminating conflicts between care bits and power management requirements.
3Loss of time
If test compression techniques are applied to reduce test data, then test time and memory requirements are reduced, but the number of scan channels increases creating thermal hot spots
Solution Approach 1:
The patent applies local quality by distributing scan channels across different physical regions of the integrated circuit rather than concentrating them in one area. The system considers the physical layout when assigning scan channels to regions, ensuring that test compression operations are spatially distributed. This reduces thermal hot spots by spreading out the thermal load across multiple regions while still achieving test compression benefits.
Data Source
AI summary
Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.