2D-Channel Transistor with Asymmetric Contacts for Short-Channel Control
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Solution Overview
Problem
Conventional two-dimensional field-effect transistors face challenges such as short-channel effects due to drain side coupling to the gate, which affect device performance and design targets in advanced semiconductor technologies.
Innovation Solution
A semiconductor device with a channel layer formed of two-dimensional material or carbon nanotubes, featuring a planar FET structure or multi-gate devices like FinFETs, where the gate structure surrounds the channel region on multiple sides, and includes embedded metal features to redistribute or terminate electric field coupling from the drain contact to the gate, reducing drain-to-gate coupling and improving short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional two-dimensional FET structure is used, then fabrication is simpler, but drain-to-gate coupling increases causing short-channel effects
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric substrate contact structure where the source contact is directly connected to the substrate while the drain contact is separated by a dielectric layer. This asymmetric configuration redistributes the electric field coupling, reducing drain-to-gate coupling and mitigating short-channel effects while maintaining fabrication feasibility through sequential contact formation processes
2Reliability
If multi-gate devices are introduced, then gate control is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing multi-gate structures selectively in regions where enhanced gate control is required, while maintaining simpler planar FET structures in other regions. This allows optimization of gate control performance in specific areas without unnecessarily increasing the complexity of the entire device architecture
3Reliability
If drain contact is separated from substrate, then short-channel effects are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the drain contact and its underlying dielectric layer structure before forming the source contact. This sequential formation process establishes the asymmetric configuration in advance, ensuring proper spatial separation and reducing drain-to-gate coupling while managing manufacturing precision requirements through controlled process sequencing
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.