2D1R Memory Cell Structure for High Current and Low Leakage
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Solution Overview
Problem
Conventional RRAM units, such as 1T1R and 1D1R structures, fail to meet design requirements for high SET and RESET currents, small size, and low leakage at device sizes below 40 nm, due to inadequate drive current and unipolar diode limitations.
Innovation Solution
A memory cell structure incorporating two diodes and a resistive random access memory element, where one diode forms a SET path and the other a RESET path, allowing for higher forward current and reduced leakage, enabling a bipolar RRAM operation with smaller diode sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1R structure is used, then RRAM cell can be formed, but transistor size becomes 10 times larger than required and leakage current increases 0.5 to 1 time higher than target
Solution Approach 1:
The patent divides the memory cell into two separate diodes (first diode for SET path, second diode for RESET path) instead of using a single transistor. This segmentation allows each diode to be optimized for specific functions, reducing the overall device size while maintaining reliability.
Solution Approach 2:
The patent replaces the transistor-based 1T1R structure with a diode-based 2D1R structure. This substitution eliminates the need for complex transistor gates and channels, significantly reducing device size and simplifying the overall architecture while achieving the same memory cell functionality.
2Reliability
If 1T1R structure is used, then RRAM cell can be formed, but leakage current becomes 0.5 to 1 time higher than target value
Solution Approach 1:
By separating the SET and RESET functions into two distinct diodes, the patent enables independent optimization of current paths. The first diode handles SET current while the second diode handles RESET current, preventing leakage current from affecting both operations simultaneously and reducing overall leakage by approximately 10 times compared to 1T1R structures.
3Ease of operation
If unipolar diode is used in 1D1R structure, then diode can pass high current in one direction, but bipolar RRAM cannot be operated with proper SET and RESET currents
Solution Approach 1:
The patent creates separate current paths for SET and RESET operations using two diodes with opposite polarities. The first diode conducts during SET operation while the second diode conducts during RESET operation, enabling full bipolar RRAM functionality while maintaining simple diode-based current conduction in each path.
Solution Approach 2:
The patent uses two diodes with opposite polarities (one oriented for forward conduction during SET, the other oriented for forward conduction during RESET). This inverted arrangement of diode orientations enables the bipolar RRAM to operate correctly by allowing current to flow in opposite directions through different diode paths.
4Length of moving object
If device size is shrunk to 40 nm and below, then scaling is achieved, but 1T1R and 1D1R structures cannot meet design requirements for high SET and RESET currents
Solution Approach 1:
By dividing the current paths into two separate diode-based paths, the patent enables each diode to be sized appropriately for its specific function even at 40 nm scale. This segmentation maintains high current capability for both SET and RESET operations while achieving the required device size reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2D1R structure increases forward drive current to the mA range, decreases leakage current to the pA range, and allows for smaller memory cell sizes, effectively addressing the limitations of conventional RRAM units.
Implementation Method 1
The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line.
Data Source
AI summary
A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.