Solid-State Devices TRIZ Cases

A display panel adjusts drain electrode overlap to maintain consistent voltage distribution across transistors.

A 2D1R memory cell structure uses two diodes to form separate set and reset paths through a resistive element.

Stepped through holes improve alignment film solution entry, reducing application unevenness and enhancing brightness uniformity in high-density displays.

M(L1)(L2) metal complexes emit saturated colors in organic light-emitting diodes, eliminating energy losses from absorption filters.

Heavily doped resin layer merges pixel electrode and defining structure, reducing fabrication complexity and ITO consumption.

Epitaxial growth forms single crystal silicon layers on SOI wafers to reduce impurity variations and crystal defects.

An intermediate layer between phosphorescent and fluorescent layers manages charge transport in organic light-emitting devices.

Alternating inorganic and organic layers minimize reflection losses while the convex high refractive index layer collimates light to boost emission efficiency.

Ultrasonic element layer on display substrate enables fingerprint sensing without silicon wafer fabrication costs.

Matching refractive index of thixotropic agents to LED encapsulants eliminates light scattering and boosts emission efficiency.

A display panel uses green light-emitting elements and conversion layers to produce red and blue sub-pixels without color filters.

A pocket implant field-effect transistor uses a graded doping profile to form a lateral NPN structure that enhances current gain.

A vertical channel transistor shifts a metal word line toward the pillar structure to reduce total sheet resistance by 90 percent.

Connecting an auxiliary electrode through a metal formation inhibiting layer minimizes sheet resistance and voltage drop in large-area displays.

A grooved semiconductor substrate increases electrode contact area through localized light heating to reduce interface resistance.

Stacking storage capacitor electrodes vertically within an array substrate increases capacitance without expanding the lateral footprint.

A conductive foil substrate with low sheet resistance drives large-area organic light-emitting diodes.

Perpendicular trench structures enable high-density on-chip integration, resolving chip space constraints without external components.

Bidirectional scanning from periphery to center inhibits displacement of modified regions from the planned cutting line, preventing oblique chip cross-sections.

A semiconductor sidewall mask process uses stacked covering layers to form parallel patterns with different widths.

Dynamic switching mechanism isolates ESD protection from data lines, preventing signal degradation while enabling dual-purpose pad functionality.

Curved filling patterns scatter light to prevent color mixture and boost brightness in organic light-emitting displays.

Field-induced orientation of sol-gel precursors creates a 5-50 μm polarizing layer that resolves the thickness-strength trade-off in flexible OLED displays.

Removing the metal gate portion over the body contact region increases effective dielectric thickness, reducing parasitic capacitance that degrades performance.

Sequential ONO and polysilicon deposition with planarization defines 1.5T SONOS gate structures, reducing photomask count and decoupling logic manufacturing.

Column-direction common electrode lines remove row-direction conflicts to enhance aperture ratio and reduce greenish phenomenon in display panels.

A semiconductor memory device uses asymmetric electrode pads to enhance electrical connectivity within vertical stack structures.

Gradient polymer density in the light outcoupling layer improves light extraction while preventing pixel blurring from surface corrugation.

A vertical bipolar transistor structure integrates conduction and control terminals within a dielectric stack to minimize memory cell footprint.

A top-emitting OLED cathode uses a magnesium-silver alloy buffer layer to protect organic functional layers during transparent metal oxide deposition.

Graded index lenses and cross-taper couplers reduce coupling losses below 0.5 dB while maintaining alignment tolerance of ±1 μm.

A sub-thin film transistor with a light transmissive sub-gate enlarges the irradiation area to generate higher photocurrent.

A two-step selective epitaxial growth process forms elevated source/drain regions with controlled interface characteristics.

A Fresnel lens layer on an OLED substrate converges light from pixel units, resolving uneven distribution and limited viewing angles.

Varying vertical distances between colored chips and the molding layer compensate for viewing angle dependencies to maintain uniform color temperature.

A light reflection member overlaps a portion of an organic emission layer to reflect visible rays and enhance luminescent efficiency.

Optimizing sensor orientation angles in a display panel notch resolves poor pressure signal detection intensity caused by altered strain directions.

A mesh structure covers exposed substrate areas between micro-LED chips to reduce external light reflection and improve display contrast.

An auxiliary electrode connects to a second electrode in a two-stack organic light emitting layer structure.

Extending protection to lateral sides blocks water and oxygen permeation along laser cut lines, enhancing flexible display panel reliability.

A storage device incorporates an intermediate layer containing silicon, germanium, tellurium, and aluminum to lower the switching element threshold voltage.

A magnetic device employs a spin sinker to attenuate self-generated spin currents, resolving the trade-off between thermal stability and spin torque efficiency.

A memory selector employs a two-dimensional material layer to modulate Schottky barrier heights at metal electrode interfaces.

Overlapping insulated scan lines reduce landing area to increase aperture ratio and lower power consumption in TFT-LCD displays.

Dual-directional trench etching exposes active layer bottoms to establish electrical connections, resolving precision trade-offs in array density.

A UV semiconductor device uses a patterned tunnel junction and reflecting layer to reduce ohmic contact resistance and eliminate p-GaN light absorption.

A coating-type organic electroluminescent device integrates an electron injection layer to enable consistent atmospheric pressure manufacturing.

An insulating film contacts the encapsulating layer to simplify fabrication and reduce panel thickness.

An OLED emissive layer with optimized host and emitter energies drives triplet-triplet fusion while suppressing singlet-triplet annihilation losses.