Semiconductor Memory Device With Asymmetric Electrode Pads
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in increasing integration density due to the need for expensive equipment for miniaturization, prompting the development of three-dimensional semiconductor memory devices with improved reliability and integration density.
Innovation Solution
A semiconductor memory device with a peripheral logic structure and stack structures featuring electrode separation regions and through electrodes, where the first electrode pad protrudes beyond the second electrode pad in both directions, and vertical structures penetrating the stack structure for enhanced electrical connectivity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar semiconductor device structure is used, then manufacturing process is simpler, but integration density cannot be increased beyond certain limit
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by forming vertical channel structures that extend in the thickness direction. Stack structures are vertically stacked above peripheral logic structures, utilizing the third dimension (height) to increase integration density without requiring further miniaturization of planar features.
2Quantity of substance
If expensive miniaturization equipment is used for 2D device, then integration density can be increased, but manufacturing cost increases significantly
Solution Approach 1:
Instead of continuing to miniaturize two-dimensional patterns which requires expensive equipment, the patent forms three-dimensional stack structures vertically stacked above peripheral logic. This approach increases integration density by utilizing vertical space rather than requiring further planar miniaturization, thereby avoiding the need for costly advanced lithography equipment.
3Quantity of substance
If three-dimensional stack structures are formed, then integration density increases, but electrical connectivity and reliability become more challenging
Solution Approach 1:
The stack structures are segmented into multiple electrode pads (first electrode pad and second electrode pad) at different heights. Through electrodes are formed to electrically connect these segmented electrodes vertically, and bitlines extend horizontally to connect to peripheral logic. This segmentation with dedicated connection paths ensures reliable electrical connectivity throughout the three-dimensional structure.
Solution Approach 2:
Through electrodes act as intermediaries to electrically connect the first electrode pad and second electrode pad within the stack structure. Bitlines serve as intermediaries to connect the stack structures to the peripheral logic structures. These intermediary elements ensure reliable electrical connectivity across the three-dimensional architecture.
4Reliability
If electrode pads are made asymmetric with different protrusion widths, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first electrode pad and second electrode pad are formed with asymmetric dimensions where the first electrode pad protrudes beyond the second electrode pad by a first width in the first direction and by a second width in the second direction, with the first width being different from the second width. This asymmetric design optimizes electrical connectivity by providing different connection interfaces in different directions, while the patent addresses the manufacturing precision challenge through a consistent formation process that simultaneously defines both dimensions.
Data Source
AI summary
A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.